The industry has been stuck on PCIe 3.0 for roughly seven years, and even though the first support for PCIe 4.0 on the desktop will land soon in AMD's third-gen Ryzen chips and the first PCIe 4.0 SSDs just cropped up, the industry is already adopting PCIe 5.0. The new standard doubles throughput over PCIe 4.0, yielding a data rate of 32 GT/s.
Today PCI-SIG, the organization that defines PCIe standards, announced that it ratified Version 0.9 of the PCI Express 5.0 specification, signaling that end devices will come to market in the near future. (Companies design end devices as early as revision 0.4 and often launch with 0.9.)
[...] PCIe 4.0 brings 64GBps of throughput, while PCIe 5.0 will double that to 128GBps. Both revisions still use the 128b/130b encoding scheme that debuted with PCIe 3.0. PCI-SIG representatives said they are satisfied with the 20% reduction in overhead facilitated by the 128b/130b encoding, and further encoding refinements to reduce the current 1.5% overhead are subject to a diminishing point of returns.
PCIe 5.0 also brings other features, like electrical changes to improve signal integrity, backward-compatible CEM connectors for add-in cards, and backward compatibility with previous versions of PCIe. The PCI-SIG also designed the new standard to reduce latency and tolerate higher signal loss for long-reach applications.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
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http://www.tomshardware.com/news/pcie-4.0-5.0-pci-sig-specfication,35325.html
PCIe is the ubiquitous engine that pulls a big part of the computing locomotive down the track—it touches nearly every device in your computer. As such, it is the linchpin for the development of many other technologies, such as storage, networking, GPUs, chipsets, and many other devices. Considering its importance, it isn't surprising to find the PCI-SIG with 750 members worldwide. Unfortunately, large organizations tend to move slowly, and PCIe 4.0 is undoubtedly late to market. PCIe 3.0 debuted in 2010 within the normal four-year cadence, but PCIe 4.0 isn't projected to land in significant quantities until the end of 2017—a seven-year gap.
PCI-SIG representatives attributed part of the delay to industry stagnation. The PCIe 3.0 interface was sufficient for storage, networking, graphics cards, and other devices, for the first several years after its introduction. Over the last two years, a sudden wellspring of innovation exposed PCIe 3.0's throughput deficiencies. Artificial intelligence craves increased GPU throughput, storage devices are migrating to the PCIe bus with the NVMe protocol, and as a result, networking suddenly has an insatiable appetite for more bandwidth.
The industry needs PCIe 4.0 to land soon, and PCI-SIG assures us it will ratify the new specification by the end of 2017. The sluggish ratification process hasn't hampered adoption entirely, though. Several IP vendors already offer 16GT/s controllers, and many vendors have already implemented PCIe 4.0 PHYs into their next-generation products. These companies are plowing ahead with the 0.9 revision of the specification, whereas the final ratified spec debuts at 1.0. PCI-SIG says it is accelerating the development and feedback processes, along with simplifying early specification revisions, in a bid to reduce time to market for future specifications. PCI-SIG indicates that PCIe 4.0 will be a short-lived specification because the organization has fast-tracked PCIe 5.0 for final release in 2019.
[...] AMD has slated PCIe 4.0 for 2020. We imagine Intel is also chomping at the bit to deploy PCIe 4.0 3D XPoint and NVMe SSDs, but the company remains silent on its timeline.
PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec
Following the long gap after the release of PCI Express 3.0 in 2010, the PCI Special Interest Group (PCI-SIG) set about a plan to speed up the development and release of successive PCIe standards. Following this plan, in late 2017 the group released PCIe 4.0, which doubled PCIe 3.0's bandwidth. Now less than two years after PCIe 4.0 – and with the first hardware for that standard just landing now – the group is back again with the release of the PCIe 5.0 specification, which once again doubles the amount of bandwidth available over a PCI Express link.
Built on top of the PCIe 4.0 standard, the PCIe 5.0 standard is a relatively straightforward extension of 4.0. The latest standard doubles the transfer rate once again, which now reaches 32 GigaTransfers/second. Which, for practical purposes, means PCIe slots can now reach anywhere between ~4GB/sec for a x1 slot up to ~64GB/sec for a x16 slot. For comparison's sake, 4GB/sec is as much bandwidth as a PCIe 1.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously:
PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
Obligatory xkcd
PCI Express Bandwidth to Be Doubled Again: PCIe 6.0 Announced, Spec to Land in 2021
When the PCI Special Interest Group (PCI-SIG) first announced PCIe 4.0 a few years back, the group made it clear that they were not just going to make up for lost time after PCI 3.0, but that they were going to accelerate their development schedule to beat their old cadence. Since then the group has launched the final versions of the 4.0 and 5.0 specifications, and now with 5.0 only weeks old, the group is announcing today that they are already hard at work on the next version of the PCIe specification, PCIe 6.0. True to PCIe development iteration, the forthcoming standard will once again double the bandwidth of a PCIe slot – a x16 slot will now be able to hit a staggering 128GB/sec – with the group expecting to finalize the standard in 2021.
[...] PCIe 6.0, in turn, is easily the most important/most disruptive update to the PCIe standard since PCIe 3.0 almost a decade ago. To be sure, PCIe 6.0 remains backwards compatible with the 5 versions that have preceded it, and PCIe slots aren't going anywhere. But with PCIe 4.0 & 5.0 already resulting in very tight signal requirements that have resulted in ever shorter trace length limits, simply doubling the transfer rate yet again isn't necessarily the best way to go. Instead, the PCI-SIG is going to upend the signaling technology entirely, moving from the Non-Return-to-Zero (NRZ) tech used since the beginning, and to Pulse-Amplitude Modulation 4 (PAM4).
[...] PCIe 6.0 will be able to reach anywhere between ~8GB/sec for a x1 slot up to ~128GB/sec for a x16 slot (e.g. accelerator/video card). For comparison's sake, 8GB/sec is as much bandwidth as a PCIe 2.0 x16 slot, so over the last decade and a half, the number of lanes required to deliver that kind of bandwidth has been cut to 1/16th the original amount.
Previously: PCIe 4.0 to be Available This Year, PCIe 5.0 in 2019
Version 0.9 of the PCI Express 5.0 Specification Ratified
PCIe 5.0 Specification Finalized (yes, that was 3 weeks ago)
(Score: 2) by driverless on Wednesday January 23 2019, @07:17AM
Open your mouth.
(Score: 3, Informative) by c0lo on Wednesday January 23 2019, @07:31AM (1 child)
Data rate my ass. If you want data rate figures, express them in bit-per-second (not in Tesla-per-second, this will describe the speed of variation of a magnetic field).
Letting aside the abuse of unit notations, the 'Transfers-per-second' describes... hold for it... the transfer rate. To get to a data rate, one needs to multiply the transfer rate with the bit-width of the transfer channel.
More details [wikipedia.org] for the enquiring minds that want to pretend they know (like mine - grin).
https://www.youtube.com/watch?v=aoFiw2jMy-0 https://soylentnews.org/~MichaelDavidCrawford
(Score: 2) by Snospar on Wednesday January 23 2019, @07:52AM
Thanks for that, I just assumed they somehow garbled the units completely and was trying to decide whether "Giga-Tera- per second" was a thing.
Huge thanks to all the Soylent volunteers without whom this community (and this post) would not be possible.
(Score: 2, Interesting) by pTamok on Wednesday January 23 2019, @07:58AM (1 child)
GT/s is an informal measure of the number of information transfers per second [wikipedia.org]. Each individual lane of a PCI Express interface is bit-serial, so it corresponds to the number of bit transitions per second. As PCI Express uses an 8b/10b encoding [wikipedia.org] scheme, each 8-bit word transmitted is encoded by a 10-bit 'word' or symbol sent on the link, so the actual word transfer rate is 80% of the naïve figure obtained by dividing the bit transition rate by 8.
Data transmission rates are usually quoted after any encoding scheme has been used. Quoting the actual bit transition rates is simply a way of making the numbers look bigger for marketing. It is sometimes instructive to work out the actual useful data transferred per second over an interface (the 'goodput') to see how much raw capacity is taken up with symbol encoding and protocol overhead.
(Score: 1) by pTamok on Wednesday January 23 2019, @08:00AM
Beaten to it by c0lo.
I forgot to check my link to goodput [wikipedia.org], so I'm putting the correctly formatted one in this post.
(Score: 1, Insightful) by Anonymous Coward on Wednesday January 23 2019, @01:13PM
The TALOS II Workstation with IBM Power9 processor launched in late 2017 or early 2018 and included PCI-E 4.0 support.
(Score: 0) by Anonymous Coward on Wednesday January 23 2019, @08:14PM (1 child)
all good and well. you can have pcie4 or 5 and lots of slots and all...but doesn't it also depend on the GT/sec of the processor managing this?
if the CPU has support for pcie 4 (for example) but only has 5 GT/sec?
(Score: 1) by pTamok on Thursday January 24 2019, @07:42AM
Not if the PCIe bus is connected to memory via DMA (Direct Memory Access [wikipedia.org]) which bypasses the CPU - that is, you are not dependent on the cpu to read stuff from memory and write it to the PCIe bus. PCI (and PCIe) do implement DMA - this StackOverflow answer [soylentnews.org] gives a bit more detail - so 'all' the cpu has to do is tell the device on the PCIe bus what bit of memory to transfer., and the optimised DMA mechanism does the rest with no involvement from the cpu.