from the it-would-be-sweet-if-they-could-make-Necco-wafers dept.
ASML said last week that it planned to ship 30 extreme ultraviolet scanners in 2019, up significantly from 2018. The plan is not surprising, as demand for EUV lithography tools is rising and semiconductors manufacturers are building new fabs. In addition, ASML indicated plans to introduce a new EUV scanner that will offer a higher production throughput, the NXE: 3400C.
Last year ASML shipped (only) 18 Twinscan NXE: 3400B EUV scanners. This was slightly below its expectations, to supply 20 machines. In total, as of July 2018, there were 31 EUV scanners installed at various fabs across the world, including several machines in various semiconductor research organizations, including imec. If everything goes as planned, ASML will ship more extreme ultraviolet scanners in 2019 than it did in in years before that.
[...] Samsung Foundry has already started to use ASML's EUV equipment for production of commercial chips using its 7LPP process technology at its Fab S3.
[...] TSMC is set to start using its Twinscan NXE scanners for commercial wafers in the second half of this year to produce chips using its N7+ manufacturing technology. Initially EUV scanners will be used for non-critical layers, but their use will be expanded at the 5 nm node in 2020 – 2021.
[...] Demand for ASML's Twinscan NXE tools will be further boosted by demand from Intel and SK Hynix.
At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.
Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.
1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!
AMSTERDAM, Dec 3 (Reuters) - Semiconductor industry bellwether ASML said on Monday a fire at one of its suppliers, electronic components maker Prodrive, would lead to some product delivery delays in early 2019.
The Dutch company, a key supplier to the world's largest computer chip makers, said in a statement it did not expect any change in 2018 deliveries, and it would take several weeks to assess the overall impact to its business.
ASML makes lithography systems, machines which can cost up to 100 million euros each and are used by Samsung, Intel, TSMC and others to help map out the circuitry of semiconductors.
TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.
TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).
[*] TSMC - Taiwan Semiconductor Manufacturing Corporation
Same chip(let) size? Approximately double the core count.
Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April