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posted by martyb on Saturday February 09 2019, @06:51PM   Printer-friendly
from the YMMV dept.

Wccftech reports that Micron plans to "introduce" NAND with 8 bits (1 byte) per cell:

Back in May of 2018, Micron introduced Quad-Level (QLC) NAND tech and, surprisingly, saw their stock tumble to pricing levels of ~$30 down from ~$60. This was the result of complex NAND pricing and supply/demand factors, not just the introduction of QLC, to be clear. I have just confirmed from multiple sources and stakeholders that Micron is intending to introduce their Octa-Level (OLC) NAND either in Q1 or latest by Q2 2019.

OLC NAND would have 28 (256) states and 28-1 (255) threshold voltages, compared to just 16 states for today's QLC NAND.

3D QLC NAND SSDs arrived on the market in 2018. QLC NAND has lower write endurance, estimated at 1,000 program/erase (PE) cycles, compared to 3,000 P/E cycles for triple-level cell (TLC) NAND, 10,000 P/E cycles for multi-level cell (MLC) NAND, and 100,000 P/E cycles for single-level cell NAND. This exceeds previous expectations of 1,000 P/E cycles for TLC NAND and 100 cycles for QLC NAND. Intel's SSD 660p drives using QLC NAND are rated for only about 0.1 drive writes per day for 5 years, or about 200 TB written on a 1 TB drive. Data retention is also reduced.

In 2013, it was reported that the U.S. Intelligence Advanced Research Projects Activity (IARPA) funded Crocus Technology development of 8-bits-per-cell Magnetic Logic Unit (MLU) memory, which would use two 4-bit layers:

Douglas Lee, VP for system strategy and corporate product development at Crocus, pointed out NAND and MRAM bits-per-cell limitations: "The current semiconductor non-volatile memory state-of-the-art is 3-4 bits per cell, as achieved in NAND flash memory, and is reaching the physical limits of floating gate memory technology. The current state-of-the-art in MRAM is only 1 bit per cell storage."


Original Submission

Related Stories

Startup Showcases 7 bits-per-cell Flash Storage with 10 Year Retention 16 comments

Startup Showcases 7 bits-per-cell Flash Storage with 10 Year Retention

Floadia Corp., a Series C startup from Japan, issued a press release this week to state that it has developed st­­orage technology capable of seven bits-per-cell (7bpc). Still in the prototype stage, this 7bpc flash chip, likely in a WORM [(Write Once Read Many)] scenario, has an effective 10-year retention time for the data at 150C. The company says that a standard modern memory cell with this level of control would only be able to [retain] the data for around 100 seconds, and so the secret in the design is to do with a new type of flash cell they have developed.

The SONOS cell uses a distributed charge trap design relying on a Silicon-Oxide-Nitride-Oxide-Silicon layout, and the company points to an effective silicon nitride film in the middle where the charges are trapped to allow for high retention. In simple voltage program and erase cycles, the company showcases 100k+ cycles with a very low voltage drift. The oxide-nitride-oxide layers rely on SiO2 and Si3N4, the latter of which is claimed to be easy to manufacture. This allows a non-volatile SONOS cell to be used in NV-SRAM or embedded designs, such as microcontrollers.

It's actually that last point which means we're a long time from seeing this in modern NAND flash. Floadia is currently partnering with companies like Toshiba to implement the SONOS cell in a variety of microcontrollers, rather than large NAND flash deployments, at the 40nm process node as embedded flash IP with compute-in-memory properties. Those aren't at 7 bits-per-cell yet, to the effect that the company is promoting that two cells can store up to 8-bits of network weights for machine learning inference – when we get to 8 bits-per-cell, then it might be more applicable. The 10-year retention of the cell data is where it gets interesting, as embedded platforms will use algorithms with fixed weights over the lifetime of the product, except for the rare update perhaps. Even with increased longevity, Floadia doesn't go into detail regarding cyclability at 7bpc at this time.

Press release.

Related: Is Octa-Level Cell (OLC) NAND Possible? We May Find Out This Year


Original Submission

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  • (Score: 2) by krishnoid on Saturday February 09 2019, @08:52PM (15 children)

    by krishnoid (1156) on Saturday February 09 2019, @08:52PM (#798919)

    So what's the difference between 3D V-NAND and M/T/Q/OLC ? Most of what I could find on this were marketing pieces.

    • (Score: 0) by Anonymous Coward on Saturday February 09 2019, @09:01PM (5 children)

      by Anonymous Coward on Saturday February 09 2019, @09:01PM (#798922)

      It doesn't matter because by the time Apple's done with it we'll still be paying $400 for 512 GB.

      Cheaper technology just means higher margins.

      • (Score: 2) by takyon on Saturday February 09 2019, @09:09PM (4 children)

        by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday February 09 2019, @09:09PM (#798924) Journal

        Well, if you're buying an SSD for your desktop, you can get 1 TB for about $100.

        If you're buying an iPhone, that's your own fault.

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        • (Score: 0) by Anonymous Coward on Saturday February 09 2019, @09:14PM (1 child)

          by Anonymous Coward on Saturday February 09 2019, @09:14PM (#798925)

          That price applies to iMac and Mac Mini. It's cheaper on the iPhone, oddly enough.

          • (Score: 2) by takyon on Saturday February 09 2019, @09:23PM

            by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday February 09 2019, @09:23PM (#798927) Journal

            *normal, user-upgradeable desktop

            This is like a masochist complaining about the pain (caused by running into the garden wall).

            Given the sales [businessinsider.com] decline [nytimes.com], maybe the next iPhone will add revolutionary new features such as a user-replaceable battery and microSD card slot.

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        • (Score: 2) by hendrikboom on Sunday February 10 2019, @03:41AM (1 child)

          by hendrikboom (1125) Subscriber Badge on Sunday February 10 2019, @03:41AM (#798988) Homepage Journal

          And how long will it work, considering it can be rewritten only about 1000 times?

          • (Score: 2) by takyon on Sunday February 10 2019, @04:21AM

            by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday February 10 2019, @04:21AM (#799001) Journal

            1000 cycles is fine for most home users and even many business users.

            Intel 660p has a 5 year warranty, and has a stated endurance of 0.1 DWPD, 200 TB written. Same as Crucial P1. Samsung 860 QVO has a 3 year warranty, with an endurance at 0.3 DWPD / 360 TB.

            If you wanted to kill the drive fast, you could probably come up with a way to do it. But it would probably be a convoluted scenario.

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    • (Score: 5, Informative) by takyon on Saturday February 09 2019, @09:08PM (2 children)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday February 09 2019, @09:08PM (#798923) Journal

      3D NAND (or vertical NAND / V-NAND) is stacked in layers to make a die. A typical die capacity is 512 Gb (64 GB), and the highest I know of is 1.33 Tb (166 GB). Furthermore, around 8-32 of the NAND dies can also be stacked using TSVs [wikipedia.org] to make a NAND package.

      64-96 layer 3D NAND is available today, 128 and more layers are coming.

      Each cell in the layer can store a certain number of bits. SLC = 1, MLC = 2, TLC = 3, QLC = 4, OLC = 8. So a 96-layer 3D QLC NAND device could store 33% more data than a 96-layer 3D TLC NAND device of the same size.

      https://www.anandtech.com/show/11627/toshiba-develops-3d-nand-with-tsvs-1tb-dies [anandtech.com]

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      • (Score: 2) by krishnoid on Saturday February 09 2019, @09:17PM (1 child)

        by krishnoid (1156) on Saturday February 09 2019, @09:17PM (#798926)

        So a XYZ- Level Cell doesn't refer to vertical levels, just a count of cells in the same level -- it's more like shrinking people's cubes so you can cram more of them in one building, and then you get slightly worse work longevity out of them?

        • (Score: 3, Informative) by takyon on Saturday February 09 2019, @09:28PM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday February 09 2019, @09:28PM (#798931) Journal

          Not a count of cells in the same level/layer, but the amount of bits that can be stored in the same cell.

          The count of cells in the same level would be represented by the process node, which was as low as around "15nm" for planar NAND but it went back up to maybe "40nm" for 3D. I can give more info later.

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    • (Score: 5, Informative) by KilroySmith on Saturday February 09 2019, @10:07PM (2 children)

      by KilroySmith (2113) on Saturday February 09 2019, @10:07PM (#798936)

      All flash devices have the "Cell" as the fundamental unit of storage, which is essentially a single Field Effect Transistor (FET). Let's assume that in the unprogrammed state, the FET is turned off. To program the device, some electrons are stored in the gate of the FET, which turns it on. To read it, you simply apply voltage and see if the cell conducts or not. Depending on how many electrons (how much charge) are stored in the gate, the FET has different resistances.

      M/T/Q/OLC refers to a technique of carefully controlling how many electrons are stored on the gate. For Single Level Cells (SLC), one bit is stored - there is either charge on the gate or not, and the reading electronics only have to look for on/off. For MLC, two bits of data are stored - four different amounts of charge are deposited in the gate, and when reading the electronics have to be able to differentiate four different resistances of the FET. For TLC, three bits are stored, 8 different amounts of charge are deposited, and for QLC four bits are stored with 16 different amounts of charge. OLC is 8 bits with 256 different amounts of charge.

      Vertical NAND flash simply refers to building layers of flash cells on top of each other. Old-style planar Nand flash just had an X-Y array of cells - think of a checkers board, or single-story hotel where every room is a cell. For V-Nand, we build vertically - 64-layer V-Nand is a 64 story hotel.

      So, S/M/T/Q/OLC defines how many bits are stored per cell, and V-Nand layers define how many cells are stacked on top of each other.

      • (Score: 2) by fyngyrz on Sunday February 10 2019, @01:11AM (1 child)

        by fyngyrz (6567) on Sunday February 10 2019, @01:11AM (#798968) Journal

        OLC is 8 bits with 256 different amounts of charge.

        It's worth emphasizing that we can get the same 2D density with two layers of 4 bits / cell with 16 levels of charge each. TFS indicates this was at least attempted in 2013:

        In 2013, it was reported that the U.S. Intelligence Advanced Research Projects Activity (IARPA) funded Crocus Technology [theregister.co.uk] development of 8-bits-per-cell Magnetic Logic Unit (MLU) memory, which would use two 4-bit layers:

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        • (Score: 2) by takyon on Sunday February 10 2019, @01:54AM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday February 10 2019, @01:54AM (#798972) Journal

          I don't know how applicable that is to NAND. It seems like a different kind of cell design using a shortcut that allows 8-bits-per-cell. I wanted to link it to show that something along these lines has been attempted, and quoted the text to show that 4-bits-per-cell was thought to be a limit for NAND (and it took years after that article for QLC to hit the market). Heck, something intermediate like 6-bits-per-cell should be easier, even if it doesn't give you that nice "one cell, one byte" design.

          If this news is real, I wouldn't be surprised if Micron also announces some dramatic technological development, like this one [ieee.org], that mitigates the likely downsides of OLC.

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    • (Score: 0) by Anonymous Coward on Saturday February 09 2019, @11:07PM (2 children)

      by Anonymous Coward on Saturday February 09 2019, @11:07PM (#798944)

      Basically: If you're a company storing important data, get SLC. If you just want something to boot from to make your computer faster, get TLC+. If you care about your data enough to pay extra get some MLC for that.

      • (Score: 0) by Anonymous Coward on Sunday February 10 2019, @12:10AM (1 child)

        by Anonymous Coward on Sunday February 10 2019, @12:10AM (#798957)

        AFAIK nobody even sells that anymore.

        • (Score: 0) by Anonymous Coward on Sunday February 10 2019, @05:23AM

          by Anonymous Coward on Sunday February 10 2019, @05:23AM (#799023)

          Nobody sells it to consumers. Consumers aren't the target market.

  • (Score: 4, Interesting) by takyon on Saturday February 09 2019, @09:01PM (5 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday February 09 2019, @09:01PM (#798921) Journal

    Sequential read/write speeds would probably drop considerably with OLC NAND, but a fresh and empty drive could operate in SLC, MLC, (TLC?), and QLC modes before finally switching to OLC mode. The IOPS would still be much higher than hard drives.

    Write endurance could be much lower, say 100-500 cycles, but it's not clear that this is too low for a high capacity consumer drive. If you have a 4 TB or 8 TB 3D OLC SSD, you could dump a lot of games and other large applications on there before filling it up. You would probably want to keep archived video on a separate hard drive. On the corporate side, bulky "cold" storage that doesn't get rewritten often can make sense. Facebook in particular wants very dense and cheap ($/TB) NAND storage [tomshardware.com]. For the consumer drives, data retention will probably be a bigger problem than low write endurance. If you leave it alone for a year and a half, will you lose data?

    In the past we've seen reports of "self-healing" NAND [ieee.org] with orders of magnitude more (or indefinite) endurance. If a technology like that makes it out of the lab, it could enable OLC NAND to be used more widely.

    QLC vs. TLC was a 33% increase in storage density. This is 100%, on top of other improvements that will be made, such as 128-256 layers of NAND. So you can start to dream of things like 1 petabyte 2.5" SSDs and 16 terabyte microSD cards.

    This has not been widely reported beyond Wccf, and could be fake, but hopefully we will not have to wait more than a few months to find out if it is real or not.

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  • (Score: 0) by Anonymous Coward on Saturday February 09 2019, @09:25PM (3 children)

    by Anonymous Coward on Saturday February 09 2019, @09:25PM (#798929)

    Write-only flash chips sure aren't excepted

  • (Score: 2) by takyon on Sunday February 10 2019, @03:33AM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday February 10 2019, @03:33AM (#798986) Journal

    Update [7:36 AM GMT+5, 10th Feb. 2019]: We have recieved the following statement from Micron:

    “Micron is aware of the article published on Feb. 8, 2019 in WCCFTech and confirms that its content is fabricated. The company will not comment further. Micron is a global leader in memory and storage solutions and will continue to drive innovation that delivers value to our customers.“

    Meanwhile, a third memory partner of Micron has told us that they plan to announce OLC in the first half of 2019. I stand by my reporting.

    Given that QLC hasn't been around for very long, I would expect an announcement of the technology, with products using it appearing a year later.

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