Western Digital's RISC-V "SweRV" Core Design Released For Free
Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.
The RTL design abstraction of Western Digital's RISC-V SweRV core is now available at GitHub. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital's brands to mark their work.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Unveils RISC-V Controller Design
Related Stories
From a Western Digital press release:
Western Digital Corp. (NASDAQ: WDC) announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to [...] transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs
Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs. WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers, though they was likely Arm-compatible chips – such as Arm9 and Cortex-M3 parts. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.
Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.
[...] The SweRV core has a two-way superscalar design and is a 32-bit, nine-stage pipeline core, meaning several instructions can be loaded at once and execute simultaneously to save time. It is also an in-order core, whose relative single core performance (a simulated 4.9 CoreMark/Mhz) is expected to exceed that of many out-of-order cores, such as the Arm Cortex A15 (actual 4.72CoreMark/Mhz). Clock speeds go up to 1.8Ghz and it will be built on a
28mm[28nm] CMOS process technology.WD said it hopes open-sourcing the core will drive development of data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more. We understand WD's ambitions for using RISC-V CPUs go beyond disk and flash drive controllers.
Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Related: WD Announces Client NVMe SSDs with In-House Controllers
Qualcomm Invests in RISC-V Startup SiFive
Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.
Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.
This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.
Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.
Also at EE Times.
See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs
Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
Esperanto Technologies and SiFive look like the names to watch.
Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
UEFI Boot Support Published For RISC-V On Linux
Western Digital's Atish Patra sent out the patch series on Tuesday for adding UEFI support for the RISC-V architecture. This initial UEFI Linux bring-up is for supporting boot time services while the UEFI runtime service support is still being worked on. This RISC-V UEFI support can work in conjunction with the U-Boot bootloader and depends upon other recent Linux kernel work around RISC-V's Supervisor Binary Interface (SBI).
Building off the common (U)EFI code within the Linux kernel, the RISC-V bring-up so far is just over four hundred lines of code. Depending upon how quickly this code is reviewed, the initial UEFI RISC-V support could land for the Linux 5.7 cycle. So far this RISC-V UEFI boot support has been tested under QEMU.
Unified Extensible Firmware Interface (UEFI).
See also: Linux EFI Going Through Spring Cleaning Before RISC-V Support Lands
Related:
Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License
(Score: 0) by Anonymous Coward on Saturday February 16 2019, @11:37AM (1 child)
Anybody doing RTL to VLSI layouts for fun? We have on-demand PCB fabrication and assembly today, are IC's and microcontrollers next?
(Score: 2) by driverless on Sunday February 17 2019, @02:51AM
Cool, a free RISC-V core in RTL. Now anyone with their own billion-dollar fab, or with tens of millions of dollars to pay an existing fab, can create their own CPUs.
(Score: 3, Interesting) by Rich on Saturday February 16 2019, @03:15PM (2 children)
- Someone at ARM must have mightily pissed them off?
- Someone at MIPS then was in deep sleep?
- Someone at WD, up to the bigwigs, must really enjoy designing new things once in a while?
When did corporate America ever come out with open hardware like this? The last time I can think of was with the original Woz designed Apple II. Or could it be that they looked at a few developments about how the storage markets develop and figured out that they'll be bust in 10 years if they just continue with what they are doing? SSD-wise they'd have no chance to source the chips in a way to stay competetive with Samsung and the Chinese, and cloud-storage wise, they'd be run over by Amazon. So they decided they might as well open a new field and become a CPU manufacturer. They'd design the initial RISC-V generation with what they'd save in ARM licenses, spread it freely until RV has enough market share to be credible, and then come out with the high-end designs the market will ask for, having the advantage of being first mover in that field?
Sounds a bit fantastic, but should their numbers show to them that spinning rust will become unfeasible in the near future, they'll need a miracle anyway.
(Score: 0) by Anonymous Coward on Saturday February 16 2019, @08:08PM
If the other guys stay with proprietary CPUs, they have a selling point for enterprise customers. Two birds with one stone - no backdoors in the storage controller, no royalties for the chips.
(Score: 2) by EETech1 on Saturday February 16 2019, @11:06PM
You must be new here!
Oh... Wait...
(Score: 0) by Anonymous Coward on Saturday February 16 2019, @04:57PM
When they are trying to save every penny on mass storage it makes perfect sense for WD to get rid of any
CPU core royalties.
(Score: 2) by Walzmyn on Sunday February 17 2019, @01:36PM
this was the quote at the bottom of the page as I read this story and comments :
"There is hardly a thing in the world that some man can not make a little worse and sell a little cheaper."
(Score: 2) by hendrikboom on Monday February 18 2019, @04:00PM
Western Digital had plans to make something like a billion RISC-V's. Not RISC-V is a royalty-free instruction set architecture, but there is a dearth of royalty-free, mass-produced chip designs. Presumably they have enough of an internal market to design their own RISC-V processor.
So even getting a free register-transfer description of their processor may be something unexpected and welcome.
Whether these chips will be useful as a SOC is another matter. They will certainly be appropriate for hiding inside disk drives.
-- hendrik
(Score: 0) by Anonymous Coward on Monday February 18 2019, @08:25PM
way to be, WD!