CXL Specification 1.0 Released: New Industry High-Speed Interconnect From Intel
With the battleground moving from single core performance to multi-core acceleration, a new war is being fought with how data is moved around between different compute resources. The Interconnect Wars are truly here, and the battleground just got a lot more complicated. We've seen NVLink[0], CCIX[1], and GenZ[2] come out in recent years as offering the next generation of host-to-device and device-to-device high-speed interconnect, with a variety of different features. Now CXL, or Compute Express Link, is taking to the field.
This new interconnect, for which the version 1.0 specification is being launched today, started in the depths of Intel's R&D Labs over four years ago, however what was made is being launched as an open standard, headed up by a consortium of nine companies. These companies include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, Intel, and Microsoft, which as a collective was described as one of the companies as 'the biggest group of influencers driving a modern interconnect standard'.
[...] While some of the competing standards have 20-50+ members, the Compute Express Link actually has more founding members than PCIe (5) or USB (7). That being said however, there are a few key names in the industry missing: Amazon, Arm, AMD, Xilinx, etc. Other standards playing in this space, such as CCIX and GenZ, have common members with CXL, and when questioned on this, the comment from CXL was that GenZ made a positive comment to the CXL press release - they stated that there is a lot of synergy between CXL and GenZ, and they expect the standards to dovetail rather than overlap. It should be pointed out that Xilinx, Arm, and AMD have already stated core CCIX support, either plausible future support or in products at some level, making this perhaps another VHS / Betamax battle. The other missing company is NVIDIA, who are more than happy with NVLink and its association with IBM.
[0] NVlink:
NVIDIA® NVLink™ technology addresses this interconnect issue by providing higher bandwidth, more links, and improved scalability for multi-GPU and multi-GPU/CPU system configurations. A single NVIDIA Tesla® V100 GPU supports up to six NVLink connections and total bandwidth of 300 GB/sec—10X the bandwidth of PCIe Gen 3.
[1] CCIX:
Cache Coherent Interconnect for Accelerators (CCIX), pronounced "see-six", is an open cache coherent interconnect architecture developed by the CCIX Consortium. CCIX is designed to simplify the communication between the central processor and the various accelerators in the system through a cache-coherent extension to standard PCIe.
[2] GenZ:
An open systems Interconnect designed to provide memory-semantic access to data and devices via direct-attached, switched or fabric topologies.
Related Stories
Intel, RISC-V Rally Rival Groups
Intel and RISC-V backers announced rival alliances to nurture competing ecosystems around tomorrow's processors.
Intel initiated Compute Express Link (CXL), an open chip-to-chip interconnect that it expects to use on its processors starting in 2021 to link to accelerators and memories. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft.
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
The CHIPS Alliance is, by far, the most ambitious of the two efforts and is just one of several open-hardware initiatives in the works at the Linux Foundation. CHIPS aims to create open-source blocks for a variety of embedded cores as well as multi-core SoCs capable of running Linux — and, ultimately, an open-source design flow to build and test them.
Also at SDxCentral.
Related: Compute Express Link Specification (CXL) Version 1.0 Launched
Startup Unisantis Proposes DRAM Alternative
Singapore-based DRAM specialist Unisantis Electronics revealed at this week's (virtual) IEEE International Memory Workshop (IMW) advances in its work on dynamic flash memory (DFM) that it claims is a faster and denser technology than DRAM or other types of volatile memory.
[...] DFM is also a type of volatile memory, but since it does not rely on capacitors it has fewer leak paths, it has no connection between switching transistors and a capacitor. The result is a cell design with the potential for significant increases in transistor density and —because it not only offers block refresh, but as a Flash memory it offers block erase — DFM reduces the frequency and the overhead of the refresh cycle and is capable of delivering significant improvements in speed and power compared to DRAM.
Using TCAD simulation, researchers at Unisantis have proven that DFM has a substantial potential to increase density 4X compared to DRAM. The scaling of DRAM has almost stopped at 16Gb, according to recent IEEE ISSCC (International Solid-State Circuits Conference) papers.
Using a PCIe Slot to Install DRAM: New Samsung CXL.mem Expansion Module
(Score: 1, Touché) by Anonymous Coward on Tuesday March 12 2019, @10:40PM
So you know spyware's baked into the spec.
(Score: 2) by MichaelDavidCrawford on Wednesday March 13 2019, @12:47AM
I was born in 1964, shortly before the Gulf Of Tonkin Incident commenced America's openly active armed involvement in Vietnam. Note that the CIA backed a coup a couple years before that, if I understand correctly it was that coup that led to a Saffron-Robed Buddhist Monk assuming the Lotus Position in the middle of a busy street, pouring five gallons of of gasoline over himself, striking a match then _meditating_.
That I did the same when a Clark County Deputy Sheriff hoped to encourage my cooperation by bending my left arm backwards led to my encouraging _his_ cooperation: he arrested me in response to my act of Satyagraha - "Nonviolence" in the fifties, "Civil Disobedience" in the sixties. I'll get back to you about what I was Civilly Disobeying, however I _will_ point out that I cost the Clark County Sheriff $2,640.00 for my jail detention alone.
Tonkin was widely regarded as having been a staged provocation.
The telegram with the news of my birth required three solid weeks to reach my father, as he was - at the time - an Enlisted Man in the United States Navy, undergoing Jungle Survival Training. This because Mindanao looks a whole lot like North Vietnam. Dad was a great lover of every cuisine, so many years later he took delight in explaining to me how to prepare Hearts Of Palm Salad by brutally murdering innocent little baby trees with his Taxpayer-Provided Bayonet.
"Hey, Mom!" I asked her one day, "Recall that Dad was in the Jungle when I was born, but that you gave the Doctor my name right away, for my birth certificate. That suggests that you and Dad must have agreed on my name before he shipped out. Did you have a name for me, were your Doctor to have shouted 'It's A Girl!'"
"Yes," she said quietly, thought but for a moment, then smiled: "Cathy Ann".
How It All Could Have Been Different.
I'm tired, there's a Starbucks across the strike whose Pike's Place Roast is calling my name. I'll complete this wall of text some other time but for now, consider:
Right around the time I was born, One Hundred Million citizens of the People's Republic Of China perished of malnutrition during a grave famine.
Right around now, Alibaba is a co-sponsor of multicore computer interconnect standards.
_This_ is why I do _not_ object in any way to foreign trade, to the offshoring even of my own jobs - and yes, I've lost tons of work, mostly to South Asians and Eastern Europeans - nor to _humanely_ treated H1B Engineers. NB: "Humane".
I have always encouraged those who aim to better themselves through the sweat of their brow, and I - respectfully - request you do so youselves.
Yes I Have No Bananas. [gofundme.com]