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posted by martyb on Saturday April 06 2019, @07:33PM   Printer-friendly
from the when-will-we-need-to-start-miniaturizing-molecules? dept.

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

Related Stories

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process 2 comments

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Samsung Plans to Make "5nm" Chips Starting in 2019-2020 5 comments

Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:

Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.

The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."

[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.

Also at AnandTech.

Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process


Original Submission

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019 13 comments

ASML to Ship 30 EUV Scanners in 2019: Faster EUV Tools Coming

ASML said last week that it planned to ship 30 extreme ultraviolet scanners in 2019, up significantly from 2018. The plan is not surprising, as demand for EUV lithography tools is rising and semiconductors manufacturers are building new fabs. In addition, ASML indicated plans to introduce a new EUV scanner that will offer a higher production throughput, the NXE: 3400C.

Last year ASML shipped (only) 18 Twinscan NXE: 3400B EUV scanners. This was slightly below its expectations, to supply 20 machines. In total, as of July 2018, there were 31 EUV scanners installed at various fabs across the world, including several machines in various semiconductor research organizations, including imec. If everything goes as planned, ASML will ship more extreme ultraviolet scanners in 2019 than it did in in years before that.

[...] Samsung Foundry has already started to use ASML's EUV equipment for production of commercial chips using its 7LPP process technology at its Fab S3.

[...] TSMC is set to start using its Twinscan NXE scanners for commercial wafers in the second half of this year to produce chips using its N7+ manufacturing technology. Initially EUV scanners will be used for non-critical layers, but their use will be expanded at the 5 nm node in 2020 – 2021.

[...] Demand for ASML's Twinscan NXE tools will be further boosted by demand from Intel and SK Hynix.

Previously: ASML Says Fire at Supplier Prodrive Will Lead to Delays Early Next Year

Related: TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process


Original Submission

Samsung Completes Development of "5nm" Node; TSMC Reveals "6nm" Node 8 comments

Samsung Completes Development of 5nm EUV Process Technology

Samsung Foundry this week announced that it has completed development of its first-generation 5 nm fabrication process (previously dubbed 5LPE). The manufacturing technology uses extreme ultraviolet lithography (EUVL) and is set to provide significant performance, power, and area advantages when compared to Samsung's 7 nm process (known as 7LPP). Meanwhile, Samsung stresses that IP developed for 7LPP can be also used for chips to be made using 5LPE.

Samsung's 5 nm technology continues to use FinFET transistors, but with a new standard cell architecture as well as a mix of DUV and EUV step-and-scan systems. When compared to 7LPP, Samsung says that their 5LPE fabrication process will enable chip developers to reduce power consumption by 20% or improve performance by 10%. Furthermore, the company promises an increase in logic area efficiency of up to 25%.

One interesting technology that will eventually be on Samsung's roadmap: "gate-all-around" field effect transistors.

Meanwhile, TSMC has announced a new node, "6nm", which will allow for smaller die sizes than "7nm" with no improvements to performance or power consumption. It is also not better than the TSMC "7nm+" node, which will use extreme ultraviolet lithography:

TSMC this week unveiled its new 6 nm (CLN6FF, N6) manufacturing technology, which is set to deliver a considerably higher transistor density when compared to the company's 7 nm (CLN7FF, N7) fabrication process. An evolution of TSMC's 7nm node, N6 will continue to use the same design rules, making it easier for companies to get started on the new process. The technology will be used for risk production of chips starting Q1 2020.

TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company's N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.

See table in article.

Previously: Samsung Discusses Foundry Plans Down to "3nm"
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020


Original Submission

Another Step Toward the End of Moore's Law 16 comments

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

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  • (Score: 2) by DannyB on Saturday April 06 2019, @07:58PM (7 children)

    by DannyB (5839) Subscriber Badge on Saturday April 06 2019, @07:58PM (#825490) Journal

    How does this compare with Intel's fab technology?

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    • (Score: 1) by Catalyst on Saturday April 06 2019, @09:43PM

      by Catalyst (7542) on Saturday April 06 2019, @09:43PM (#825512)

      Well TSMC was already ahead of Intel on density with their 7mm, so presumably the 5mm is ahead even more.

    • (Score: 0) by Anonymous Coward on Saturday April 06 2019, @10:14PM (5 children)

      by Anonymous Coward on Saturday April 06 2019, @10:14PM (#825523)

      It should beat Intel 10nm at least. Maybe not Intel 7nm.

      • (Score: 2) by JoeMerchant on Saturday April 06 2019, @10:58PM (4 children)

        by JoeMerchant (3937) on Saturday April 06 2019, @10:58PM (#825536)

        What kind of math is that? Intel 7nm is higher density than TSMC 5nm?

        The more interesting battle might be in multi-layer and full 3D structures. If you can stack 100+ ultra-thin layers, even if the feature size is 20nm, that's going to be extreme density. Even if the cooling problem isn't solved, this kind of structure could do the work of 100s of equivalent 100% duty cycle parts, meaning an instant answer to a hard question - followed by 99% downtime to cool off...

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        • (Score: 0) by Anonymous Coward on Sunday April 07 2019, @01:22AM (1 child)

          by Anonymous Coward on Sunday April 07 2019, @01:22AM (#825582)

          nm chip die sizes are marketing bullshit these days. Intel and TSMC measure different things.

          • (Score: 2) by DannyB on Monday April 08 2019, @01:35PM

            by DannyB (5839) Subscriber Badge on Monday April 08 2019, @01:35PM (#826140) Journal

            Remember back in the day when everyone compared MHz and later GHz? Isn't an Intel GHz exactly the same thing as an AMD GHz? And aren't they exactly the same and consistent even within a single manufacturer's product lines?

            What? No!?!?!

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        • (Score: 2) by takyon on Sunday April 07 2019, @03:43AM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday April 07 2019, @03:43AM (#825626) Journal

          As stated, the number is not meaningful, particularly when comparing between Intel, Samsung, TSMC, etc.

          Just think of Intel 14nm++++ as "Intel A v5", Intel 10nm as "Intel B v1". The numbers are just labels. Then you can find the stats to compare various processes. TSMC's 7FF+ supposedly will use 90% of the power of TSMC 7FF, for about the same performance, and 83% of the area for the same amount of transistors. TSMC 5FF is 80% power, 115% performance, and 55% of the area compared to TSMC 7FF. So 5FF should be about 89% power, 115% perf, and 66% area of 7FF+.

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        • (Score: 2) by takyon on Sunday April 07 2019, @12:09PM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Sunday April 07 2019, @12:09PM (#825738) Journal

          About the 3D stuff:

          1. Neuromorphic chips with very low power consumption (due to acting more like the human brain) could benefit first. Layered GPUs could be seen long before CPUs.

          2. A new transistor type [soylentnews.org] (there are several candidates [wikipedia.org]) could reduce heat, making layering feasible.

          3. On-chip optics and DRAM placed close to CPU in 3D structure could help.

          4. Continuing down to/past the limits of lithography (possibly requiring technologies like self-assembly) will be rewarding, improving our ability to create (other) nanotechnologies.

          5. To the extent that the "X-nanometer" labels even mean anything, the industry still has some room to scale down, likely to at least one or two nodes smaller than TSMC's "5nm":

          Transistor Options Beyond 3nm [semiengineering.com]

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  • (Score: 0) by Anonymous Coward on Sunday April 07 2019, @06:33AM

    by Anonymous Coward on Sunday April 07 2019, @06:33AM (#825678)

    if you've seen one nanometer, you've seen one nanometer

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