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posted by martyb on Friday April 19 2019, @04:59PM   Printer-friendly
from the 5nm-is-45-silicon-atoms-@-111pm-each dept.

Samsung Completes Development of 5nm EUV Process Technology

Samsung Foundry this week announced that it has completed development of its first-generation 5 nm fabrication process (previously dubbed 5LPE). The manufacturing technology uses extreme ultraviolet lithography (EUVL) and is set to provide significant performance, power, and area advantages when compared to Samsung's 7 nm process (known as 7LPP). Meanwhile, Samsung stresses that IP developed for 7LPP can be also used for chips to be made using 5LPE.

Samsung's 5 nm technology continues to use FinFET transistors, but with a new standard cell architecture as well as a mix of DUV and EUV step-and-scan systems. When compared to 7LPP, Samsung says that their 5LPE fabrication process will enable chip developers to reduce power consumption by 20% or improve performance by 10%. Furthermore, the company promises an increase in logic area efficiency of up to 25%.

One interesting technology that will eventually be on Samsung's roadmap: "gate-all-around" field effect transistors.

Meanwhile, TSMC has announced a new node, "6nm", which will allow for smaller die sizes than "7nm" with no improvements to performance or power consumption. It is also not better than the TSMC "7nm+" node, which will use extreme ultraviolet lithography:

TSMC this week unveiled its new 6 nm (CLN6FF, N6) manufacturing technology, which is set to deliver a considerably higher transistor density when compared to the company's 7 nm (CLN7FF, N7) fabrication process. An evolution of TSMC's 7nm node, N6 will continue to use the same design rules, making it easier for companies to get started on the new process. The technology will be used for risk production of chips starting Q1 2020.

TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company's N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.

See table in article.

Previously: Samsung Discusses Foundry Plans Down to "3nm"
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020


Original Submission

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Samsung Discusses Foundry Plans Down to "3nm" 14 comments

Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019

Samsung recently hosted its Samsung Foundry Forum 2018 in Japan, where it made several significant foundry announcements. Besides reiterating plans to start high-volume manufacturing (HVM) using extreme ultraviolet lithography (EUVL) tools in the coming quarters, along with reaffirming plans to use gate all around FETs (GAAFETs) with its 3 nm node, the company also added its brand-new 8LPU process technology to its roadmap. Samsung Foundry's general roadmap was announced earlier this year, so at SFF in Japan the contract maker of semiconductors reiterated some of its plans, made certain corrections, and provided some additional details about its future plans.

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

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  • (Score: 4, Interesting) by bzipitidoo on Friday April 19 2019, @05:57PM (3 children)

    by bzipitidoo (4388) on Friday April 19 2019, @05:57PM (#832225) Journal

    Sounds great, but seems to take a couple of years for these improvements to trickle down to commodity computers. Wish it was a bit faster. I only recently upgraded to 14nm stuff, from 45nm.

    And hasn't there been a shortage of 14nm chips recently, forcing a bit of 22nm product sales and use?

    Let's see, what's my wish list again? 7nm or smaller, Spectre fixed, AV1 hardware accelerated decoding (encoding would be nice to have too), and for the garbage x86 architecture full virtualization support that will make VirtualPC and VMWare and dual boot unnecessary.

    • (Score: 2) by takyon on Friday April 19 2019, @06:30PM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday April 19 2019, @06:30PM (#832235) Journal

      AV1 hardware accelerated decoding (encoding would be nice to have too)

      That sounds familiar.

      I might pick up a cheap "14nm" machine (trying to nab a BrickSeek deal right now) and then skip some nodes. TSMC "5nm" (5FF) promises 45% area reduction which could translate into another core count doubling. If it doesn't for the smaller chips, space savings could be spent on much larger integrated GPUs. Around that node (Zen 4 - Zen 5), AMD may make some design choices that lower the power consumption floor (stacked DRAM, for instance).

      Unfortunately it looks like Intel, AMD, et al. will run out the clock on planar CPUs, down to "3nm" or below, and only after a decade do we have a chance of seeing orders of magnitude performance increase from a 3D SoC.

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    • (Score: 2) by tibman on Friday April 19 2019, @08:49PM

      by tibman (134) Subscriber Badge on Friday April 19 2019, @08:49PM (#832286)

      Only a couple of months for consumer CPUs. The Ryzen 3k series (Zen 2) is 7nm and is already sampling. Should be for sale June-ish. https://en.wikipedia.org/wiki/Zen_2 [wikipedia.org]

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    • (Score: 1) by Coward, Anonymous on Friday April 19 2019, @11:23PM

      by Coward, Anonymous (7017) on Friday April 19 2019, @11:23PM (#832364) Journal

      Give them credit for advancing EUV. The technology is amazing.

  • (Score: -1, Offtopic) by Anonymous Coward on Friday April 19 2019, @08:55PM (3 children)

    by Anonymous Coward on Friday April 19 2019, @08:55PM (#832289)

    Zzz ...

    • (Score: -1, Offtopic) by Anonymous Coward on Friday April 19 2019, @11:35PM (2 children)

      by Anonymous Coward on Friday April 19 2019, @11:35PM (#832368)

      Sorry, I will clarify my post: stories about process shrinks are the most boring stories in the world, like play by play coverage of paint drying.
      It's my opinion, you may not agree with it, but it is on topic.

      • (Score: 2) by takyon on Saturday April 20 2019, @08:31AM (1 child)

        by takyon (881) <takyonNO@SPAMsoylentnews.org> on Saturday April 20 2019, @08:31AM (#832483) Journal

        That may be true, for you.

        On the other hand, if another technology improves 5%, 10%, 20%, or 45% in some aspect, it could be front page news with billion or trillion dollar implications. We have gotten too used to the free lunch of the past and don't appreciate these "small" gains.

        Maybe when 3D SoCs get commercialized in a few years/a decade you'll be less bored.

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        • (Score: 1, Informative) by Anonymous Coward on Saturday April 20 2019, @09:21PM

          by Anonymous Coward on Saturday April 20 2019, @09:21PM (#832710)

          I never said it wasn't a worthy achievement.
          I just said it was boring. Accounting, as an example, is vital to keeping a business running. But stories about it all sound the same.

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