from the 5nm-is-45-silicon-atoms-@-111pm-each dept.
Samsung Foundry this week announced that it has completed development of its first-generation 5 nm fabrication process (previously dubbed 5LPE). The manufacturing technology uses extreme ultraviolet lithography (EUVL) and is set to provide significant performance, power, and area advantages when compared to Samsung's 7 nm process (known as 7LPP). Meanwhile, Samsung stresses that IP developed for 7LPP can be also used for chips to be made using 5LPE.
Samsung's 5 nm technology continues to use FinFET transistors, but with a new standard cell architecture as well as a mix of DUV and EUV step-and-scan systems. When compared to 7LPP, Samsung says that their 5LPE fabrication process will enable chip developers to reduce power consumption by 20% or improve performance by 10%. Furthermore, the company promises an increase in logic area efficiency of up to 25%.
One interesting technology that will eventually be on Samsung's roadmap: "gate-all-around" field effect transistors.
Meanwhile, TSMC has announced a new node, "6nm", which will allow for smaller die sizes than "7nm" with no improvements to performance or power consumption. It is also not better than the TSMC "7nm+" node, which will use extreme ultraviolet lithography:
TSMC this week unveiled its new 6 nm (CLN6FF, N6) manufacturing technology, which is set to deliver a considerably higher transistor density when compared to the company's 7 nm (CLN7FF, N7) fabrication process. An evolution of TSMC's 7nm node, N6 will continue to use the same design rules, making it easier for companies to get started on the new process. The technology will be used for risk production of chips starting Q1 2020.
TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company's N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.
See table in article.
Samsung recently hosted its Samsung Foundry Forum 2018 in Japan, where it made several significant foundry announcements. Besides reiterating plans to start high-volume manufacturing (HVM) using extreme ultraviolet lithography (EUVL) tools in the coming quarters, along with reaffirming plans to use gate all around FETs (GAAFETs) with its 3 nm node, the company also added its brand-new 8LPU process technology to its roadmap. Samsung Foundry's general roadmap was announced earlier this year, so at SFF in Japan the contract maker of semiconductors reiterated some of its plans, made certain corrections, and provided some additional details about its future plans.
TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.
TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).
[*] TSMC - Taiwan Semiconductor Manufacturing Corporation
Same chip(let) size? Approximately double the core count.
Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April