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posted by martyb on Monday June 03 2019, @06:14AM   Printer-friendly
from the and-then-there-were-two dept.

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

Related Stories

TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020 3 comments

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


Original Submission

TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process 2 comments

TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains

At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company's second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML's Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC's 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

1.8x higher transistor density and up to 15% frequency gain or 20% power reduction? You should be thankful you're getting anything!

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020


Original Submission

Samsung Plans to Make "5nm" Chips Starting in 2019-2020 5 comments

Samsung is preparing to manufacture 7LPP and 5LPE process ARM chips:

Samsung has said its chip foundry building Arm Cortex-A76-based processors will use 7nm process tech in the second half of the year, with 5nm product expected mid-2019 using the extreme ultra violet (EUV) lithography process.

The A76 64-bit chips will be able to pass 3GHz in clock speed. Back in May we wrote: "Arm reckoned a 3GHz 7nm A76 single core is up to 35 per cent faster than a 2.8GHz 10nm Cortex-A75, as found in Qualcomm's Snapdragon 845, when running mixed integer and floating-point math benchmarks albeit in a simulator."

[...] Samsung eventually envisages moving to a 3nm Gate-All-Round-Early (3AAE) on its process technology roadmap. Catch up, Intel, if you can.

Also at AnandTech.

Previously: Samsung Roadmap Includes "5nm", "4nm" and "3nm" Manufacturing Nodes

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap (obsolete)
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process


Original Submission

TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April 13 comments

TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019

Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.

TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).

[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).

TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.

Tape-out. Risk production = early production.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process

Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack


Original Submission

TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020 9 comments

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


Original Submission

Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan 17 comments

Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:

Intel's New Chip Wizard Has a Plan to Bring Back the Magic (archive)

In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.

[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.

The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law


Original Submission

TSMC Shows Off Gigantic Silicon Interposer 14 comments

TSMC Shows Colossal Interposer, Says Moore's Law Still Alive

In the company's first blog post, TSMC has stated that Moore's Law is still alive and well, despite the zeitgeist of recent times being the reverse. The company also showed a colossal 2500mm2 interposer that includes eight HBM memory chips and two big processors.

Godfrey Cheng, TSMC's new head of global marketing, wrote the blog post. He notes that Moore's Law is not about performance, but about transistor density. While performance traditionally improved by increasing the clock speed and architecture, today it is more often improved by increasing parallelization, and hence requires increases in chip size. This enhances the importance of transistor density because chip cost is directly proportional to its area.

[...] "one possible future of great density improvements is to allow the stacking of multiple layers of transistors in something we call Monolithic 3D Integrated Circuits. You could add a CPU on top of a GPU on top of an AI Edge engine with layers of memory in between. Moore's Law is not dead, there are many different paths to continue to increase density."

[...] [System-technology co-optimization (STCO)] is done through advanced packaging, for which TSMC supports silicon-based interposers and fan-out-based chiplet integration. It also has techniques to stack chips on wafers, or stack wafers on top of other wafers. As one such example, TSMC showed a nearly-2500mm2 silicon interposer – the world's largest – on top of which two 600mm2 processors are placed and eight 75mm2 HBM memory chips, which makes for 1800mm2 of compute and memory silicon on top of the interposer-based package, well over two times the conventional reticle size limit.

Related: Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Performance
Another Step Toward the End of Moore's Law
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan


Original Submission

Is Moore’s Law Actually Dead This Time? Nvidia Seems to Think So 23 comments

Chips "going... down in price is a story of the past," CEO says:

When Nvidia rolled out its new RTX 40-series graphics cards earlier this week, many gamers and industry watchers were a bit shocked at the asking prices the company was putting on its latest top-of-the-line hardware. New heights in raw power also came with new heights as far as MSRP, which falls in the $899 to $1,599 range for the 40-series cards.

When asked about those price increases, Nvidia CEO Jensen Huang told the gathered press to, in effect, get used to it. "Moore's law is dead," Huang said during a Q&A, as reported by Digital Trends. "A 12-inch wafer is a lot more expensive today. The idea that the chip is going to go down in price is a story of the past."

[...] Generational price comparisons aside, Huang's blanket assertion that "Moore's law is dead" is a bit shocking for a company whose bread and butter has been releasing graphics cards that roughly double in comparable processing power every year. But the prediction is far from a new one, either for Huang—who said the same thing in 2019 and 2017—or for the wider industry—the International Technology Roadmap for Semiconductors formally announced it would stop chasing the benchmark in its 2016 roadmap for chip development.

[...] As Kevin Kelly laid out in a 2009 piece, though, Moore's law is best understood not as a law of physics but as a law of economics and corporate motivation. Processing power keeps doubling partly because consumers expect it to keep doubling and finding uses for that extra power.

That consumer demand, in turn, pushes companies to find new ways to keep pace with expectations. In the recent past, that market push led to innovations like tri-gate 3D transistors and production process improvements that continually shrink the size of individual transistors, which IBM can now push out at just 2 nm.

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  • (Score: 0) by Anonymous Coward on Monday June 03 2019, @06:53AM (1 child)

    by Anonymous Coward on Monday June 03 2019, @06:53AM (#850749)

    If we could use physical tri-state logic orderly to represent trits instead of bits, density and precision of computations would be proportionally increased. Unfortunately, a Shannon's curse of binary still haunts us, an apparition of two's complement...

    • (Score: 2) by maxwell demon on Monday June 03 2019, @07:20AM

      by maxwell demon (1608) Subscriber Badge on Monday June 03 2019, @07:20AM (#850756) Journal

      Unfortunately, a Shannon's curse of binary still haunts us
      Shannon used bits as measure of information, not implying that this is what you should use. No, the use of bits is because this allows simpler circuits. A basic NOT gate just needs one transistor. A basic NAND gate needs one transistor per input. I'd suspect that implementing trit gates in hardware is sufficiently complex that it at least negates the savings from needing less of them.

      --
      The Tao of math: The numbers you can count are not the real numbers.
  • (Score: 5, Informative) by takyon on Monday June 03 2019, @06:54AM (10 children)

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Monday June 03 2019, @06:54AM (#850750) Journal

    TSMC's "6nm" is a denser drop-in for the current "7nm". According to them, it will have no performance and power consumption improvements, just a bit of area scaling. It looks like it will be a bit worse than "7nm+" which uses more EUV, but companies that already developed designs for "7nm" can save a few bucks.

    https://www.anandtech.com/show/14228/tsmc-reveals-6-nm-process-technology-7-nm-with-higher-transistor-density [anandtech.com]

    TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company’s N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.

    "3nm" should be the point when TSMC and Samsung transition to gate-all-around transistors.

    There could be a couple of nodes beyond that before real big changes are needed. Like these [soylentnews.org].

    https://semiengineering.com/transistor-options-beyond-3nm/ [semiengineering.com]
    https://semiengineering.com/big-trouble-at-3nm/ [semiengineering.com] (article was written before GlobalFoundries chickened out of "7nm")

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 2) by janrinok on Monday June 03 2019, @07:29AM

      by janrinok (52) Subscriber Badge on Monday June 03 2019, @07:29AM (#850757) Journal
      We can always rely on you to provide the additional information that many of us don't know. Have a mod point!
    • (Score: 2, Funny) by Anonymous Coward on Monday June 03 2019, @10:42AM (3 children)

      by Anonymous Coward on Monday June 03 2019, @10:42AM (#850789)

      What do you think about apples new $7999.99 wieghtless and completely transparent MacBook?

      • (Score: 3, Funny) by takyon on Monday June 03 2019, @10:59AM (2 children)

        by takyon (881) <takyonNO@SPAMsoylentnews.org> on Monday June 03 2019, @10:59AM (#850797) Journal

        It uses a 0nm processor, right?

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        [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
        • (Score: 0) by Anonymous Coward on Monday June 03 2019, @12:45PM (1 child)

          by Anonymous Coward on Monday June 03 2019, @12:45PM (#850834)

          Yep, 0 nm technology.

          • (Score: 2) by bob_super on Monday June 03 2019, @05:36PM

            by bob_super (1357) on Monday June 03 2019, @05:36PM (#850919)

            Incidentally, 0nm is also the travel on the keyboard they'll put on it.
            "3D haptic feedback", they'll call it. With changeable keyboard shapes.

            Yet it will still fail because of microscopic dust, and it will be your fault.

    • (Score: 2) by Rupert Pupnick on Monday June 03 2019, @02:51PM (4 children)

      by Rupert Pupnick (7277) on Monday June 03 2019, @02:51PM (#850861) Journal

      Good stuff, thanks. So the question becomes how useful is just area scaling alone to customers that would be designing these parts into their products. Depends of course on the application, and whether you run into thermal or power consumption issues.

      • (Score: 2) by bob_super on Monday June 03 2019, @05:43PM (3 children)

        by bob_super (1357) on Monday June 03 2019, @05:43PM (#850922)

        Almost all chips can handle having a thermal interface to the copper that's 18% smaller. The problem is usually interfacing the copper to air.
        Intel would have to stop using dumb paste, but that's about it.

        On the other hand, 18% chip size reduction means significantly higher yields (more dies per wafer if constant impurities).

        While the transistors don't change, calling 6 instead 7 is actually a reasonable approach, for once.
        On the other hand, having 5nm, 6nm, 7nm, 10nm (even before Intel goes 10nm++UltraTurboAlphaPrime) is going to be confusing for anyone not knee-deep in that industry.

        • (Score: 2) by takyon on Monday June 03 2019, @08:38PM (2 children)

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Monday June 03 2019, @08:38PM (#850984) Journal

          If there aren't any thermal problems, more chiplets could be stuffed onto a board. Epyc uses 8 for 64 cores, rumor has it that it could be increased to 10+.

          --
          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
          • (Score: 2) by bob_super on Monday June 03 2019, @08:51PM (1 child)

            by bob_super (1357) on Monday June 03 2019, @08:51PM (#850992)

            You can keep adding chiplets as long as you find a way to bring more Amps in, and take more Watts out, of the socket.
            The chiplet size is not the most important factor. Cu is a great conductor, and solder is pretty good. Intel caused trouble with their shitty solder paste, making big die sizes actually better, but using proper methods, the conductivity is so much better that die size is nowhere near the system's limiting factor.

            You also need to make sure you don't put too many chiplets on the shared resources, or have more shared resources to avoid starvation. Each chiplet requires a good deal of connectivity, so you end up needing two separate IO chips, a small one for the cheap stuff, and a bit one to enable the extra connections. That's got a non-trivial cost.

  • (Score: 3, Insightful) by JoeMerchant on Monday June 03 2019, @12:01PM

    by JoeMerchant (3937) on Monday June 03 2019, @12:01PM (#850823)

    The respected old brand name Bosch (Intel) quotes a conservative 3.6V per 18650 LiIon cell in their power pack, marketing an 18V (5 cell) product. Meanwhile, the less conservative upstart Kobalt (TSMC/Samsung) brazenly rates their same 18650 cells at 4.0V a piece, marketing a 24V (6 cell) product.

    The Kobalt product does have superior base physics behind its performance, just not quite the margin that's claimed on the packaging. Then we can talk about the quality of the tools that these power cells drive...

    --
    Україна досі не є частиною Росії. https://www.newsweek.com/russian-state-tv-ukraine-war-dirty-bomb-putin-1754428
  • (Score: 1, Interesting) by Anonymous Coward on Monday June 03 2019, @07:14PM (1 child)

    by Anonymous Coward on Monday June 03 2019, @07:14PM (#850960)

    Moore's Law: Every 18 months, the speed of hardware doubles.

    Gates' Law: Every 18 months, the speed of software halves.

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