SoylentNews

tonyPick writes:

An article at Hackerboards is reporting the announcement that fabless semiconductor company SiFive has announced the first embedded SoCs based on the open source RISC-V platform

A VC-backed startup closely associated with the RISC-V project announced the first system-on-chip implementations of the open source RISC-V processor platform. At the RISC-V 4thWorkshop at MIT this week, SiFive announced two embedded SoC families. The Freedom Unleashed family debuts with a 28nm fabricated, Freedom U500 SoC with up to eight 1.6GHz cores that runs Linux, aimed at machine learning, storage, and networking applications. The MCU-like Freedom Everywhere family for Internet of Things starts with a 180nm Freedom E300 model that runs FreeRTOS.

Like RISC-V, both designs are fully open source, but the company also plans to sell finished SoCs with the help of fabrication partner TSMC. The platform will "reverse the industry's prohibitively rising licensing, design and implementation costs," says SiFive.

Although the SiFive announcement talks about the final SoC implementation currently only targets based on standard FPGA based development platforms appear to be available.

This earlier SN article contains more information on the RiscV project and the development of an open Instruction Set Architecture.

Original Submission

An Anonymous Coward writes:

OnChip and SiFive, two groups aiming to develop and release RISC-V platforms, have announced they will collaborate. From OnChip's crowdfunding campaign:

Sounds like good news for those hoping for RISC-V and open hardware designs to become tangible objects.
Note that the SiFive HiFive1 campaign was successful and has already shipped to some backers while the OnChip OPEN-V campaign looks like it will not reach its goal.

Original Submission

MrPlow writes:

Submitted via IRC for TheMightyBuzzard

SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced that UltraSoC will provide debug and trace technology for the SiFive Freedom platform, based on the RISC-V open source processor specification as part of the DesignShare initiative. UltraSoC's embedded analytics IP will be available through the recently announced SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. UltraSoC's debug and trace functionality will enable users of the Freedom platform to access a wide variety of tools and interfaces to use in their developments.

The DesignShare concept enables an entirely new range of applications. Companies like SiFive, UltraSoC and other ecosystem partners have developed efficient, pre-integrated solutions to lower the upfront engineering costs required to bring a custom chip design based on the SiFive Freedom platform to realization. The partnership between SiFive, originator of the industry's first open-source chip platform, and UltraSoC, the industry leader in vendor-neutral on-chip debug and analytics tools, significantly strengthens the ecosystem surrounding RISC-V, the open source processor specification which is often dubbed "the Linux of the semiconductor industry."

[...] Rick O'Connor, executive director of the RISC-V Foundation, commented: "The idea behind the open source movement is that one doesn't have to design everything from scratch. The idea behind DesignShare is to help speed the development of new silicon designs by reducing the barriers of cost, process and integration that have traditionally held back innovation in the semiconductor industry. SiFive, UltraSoC and the other companies that are making their IP available through DesignShare are fundamentally enabling this revolution in an otherwise stagnant industry."

Source: http://markets.businessinsider.com/news/stocks/SiFive-and-UltraSoC-partner-to-accelerate-RISC-V-development-through-DesignShare-1002349996

Original Submission

MrPlow writes:

Submitted via IRC for TheMightyBuzzard

Slowly but surely, RISC-V, the Open Source architecture for everything from microcontrollers to server CPUs is making inroads in the community. Now SiFive, the major company behind putting RISC-V c...

That's damned nifty but at a grand for a 1.5GHz system, I don't see them selling that many to consumers.

Source: https://hackaday.com/2018/02/03/sifive-introduces-risc-v-linux-capable-multicore-processor/

Original Submission

lordtaw writes:

Spotted over on Phoronix:

While free software/hardware advocates have been ecstatic about the RISC-V open-source, royalty-free processor architecture, hardware so far hasn't been as open as desired.

While this processor ISA is entirely open and living up to its merits, it turns out the RISC-V implementations so far haven't been quite as open as one would have thought. A Phoronix reader pointed out to us some remarks by developers on the main RISC-V development board out so far, the SiFive HiFive Unleashed

Ron Minnich who has run the Coreboot project for more than the past decade and spearheads the effort of getting Coreboot on new Chrome OS devices at Google, commented on the Unleashed development board this weekend:

All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive.

Open instruction sets do not necessarily result in open implementations. An open implementation of RISC-V will require a commitment on the part of a company to opening it up at all levels, not just the instruction set.

The issue stems from the use of third party IP used to complete the SoC as Risc-V is an instruction set, not a physical hardware design. The actual silicon of the CPU must be designed in order to implement the instruction set as actual hardware and glue logic to tie the CPU to other hardware like memory and bus controllers. In the case, the HiFive Unleashed features a DRAM controller from Cadence which uses a proprietary binary blob to initialize the DRAM controller. This makes open firmware implementations legally difficult.

Original Submission

takyon writes:

Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs

Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs. WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers, though they was likely Arm-compatible chips – such as Arm9 and Cortex-M3 parts. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.

Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.

[...] The SweRV core has a two-way superscalar design and is a 32-bit, nine-stage pipeline core, meaning several instructions can be loaded at once and execute simultaneously to save time. It is also an in-order core, whose relative single core performance (a simulated 4.9 CoreMark/Mhz) is expected to exceed that of many out-of-order cores, such as the Arm Cortex A15 (actual 4.72CoreMark/Mhz). Clock speeds go up to 1.8Ghz and it will be built on a 28mm [28nm] CMOS process technology.

WD said it hopes open-sourcing the core will drive development of data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more. We understand WD's ambitions for using RISC-V CPUs go beyond disk and flash drive controllers.

Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V

Related: WD Announces Client NVMe SSDs with In-House Controllers

Original Submission

martyb writes:

Raspberry Pi Foundation Announces RISC-V Foundation Membership:

[The Raspberry Pi] Foundation has announced that it is joining the RISC-V Foundation, suggesting that a shift away from Arm could be on the cards. "We're excited to have joined the RISC-V Foundation as a silver member," the Raspberry Pi Foundation posted to its Twitter account. "[We're] hoping to contribute to maturing the Linux kernel and Debian port for the world's leading free and open instruction set architecture."

A shift from the proprietary Arm architecture to RISC-V would fit in nicely with the Foundation's goal of low-cost, highly-accessible computing for education and industry – but would put paid to its tradition of keeping backwards compatibility where possible, something it has already suggested might be the case when it moves away from the Broadcom BCM283x platform for the Raspberry Pi 4. Foundation co-founder Eben Upton, though, is clear: the Foundation is currently focusing on supporting the ISA in software, and not with a development board launch.

I'm curious how many Soylentils have a Raspberry Pi (or more than one) and which model(s). How has your experience been? What are the positives and shortcomings you've encountered? Do you think it would be a good move for them to move to RISC-V?

More background on RISC-V is available at Wikipedia.

Original Submission

takyon writes:

Western Digital's RISC-V "SweRV" Core Design Released For Free

Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.

The RTL design abstraction of Western Digital's RISC-V SweRV core is now available at GitHub. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital's brands to mark their work.

Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
Western Digital Unveils RISC-V Controller Design

Original Submission

takyon writes:

Intel, RISC-V Rally Rival Groups

Intel and RISC-V backers announced rival alliances to nurture competing ecosystems around tomorrow's processors.

Intel initiated Compute Express Link (CXL), an open chip-to-chip interconnect that it expects to use on its processors starting in 2021 to link to accelerators and memories. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft.

Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.

The CHIPS Alliance is, by far, the most ambitious of the two efforts and is just one of several open-hardware initiatives in the works at the Linux Foundation. CHIPS aims to create open-source blocks for a variety of embedded cores as well as multi-core SoCs capable of running Linux — and, ultimately, an open-source design flow to build and test them.

Also at SDxCentral.

Related: Compute Express Link Specification (CXL) Version 1.0 Launched

Original Submission

takyon writes:

Alibaba Crafts A 16-Core RISC-V Chip @ 2.5GHz

Alibaba this week announced a RISC-V 64-bit processor comprised of 16 cores at 2.5GHz. The Chinese RISC-V CPU is fabbed at 12nm and this RISC-V processor supports out of order execution. This Alibaba design achieves a 7.1 Coremark/MHz rating, a great deal faster than any other publicly announced RISC-V processor. It's still not as fast as say the newest AMD Ryzen 9 or Intel Core i7/i9 parts, but it's certainly much better than all of the other RISC-V processors/SoCs we've seen announced to date. Unfortunately additional details on this Alibaba design are light.

Also at Tom's Hardware.

Related: Alibaba Cloud Climbs to Top 5
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance
Qualcomm Invests in RISC-V Startup SiFive

Original Submission

takyon writes:

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year's we've seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we've seen a lot of vendors make the switch from licensing Arm's architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on the ISA. While many vendors do choose to design their own microarchitectures to replace Arm-based microcontroller designs in their products, things get a little bit more complicated once you scale up in performance. It's here where SiFive comes into play as a RISC-V IP vendor offering more complex designs for companies to license – essentially a similar business model to Arm's – just that it's based on the new open ISA.

Today's announcement marks a milestone in SiFive's IP offering as the company is revealing its first ever out-of-order CPU microarchitecture, promising a significant performance jump over existing RISC-V cores, and offering competitive PPA metrics compared to Arm's products. [...] SiFive's design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. The A72 is quite an old comparison point by now, however SiFive's PPA targets are comparatively quite high, meaning the U8 should be quite competitive to Arm's latest generation cores.

Performance gains over previous designs are substantial:

The performance increases compared to previous generation SiFive cores are extremely impressive: Against a U54 at ISO-process, the new U84 features a 5.3x performance increase in SPECint2006. When taking into account the process node improvements that allow the U84 to clock higher, the generational increases that we'd be seeing in products will be more akin to a factor of 7.2x.

In terms of PPA, compared to a U7-series CPU, IPC increases come in at 2.3x resulting in 3.1x higher performance (ISO-process). A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.

On the same 7nm process, the U84 lands in at 0.28mm² per core and a cluster comprising four cores and a 2MB L2 cache measure in at 2.63mm². For comparison, an Arm Cortex-A55 as measured on the Kirin 980, also on 7nm, a core with its 128KB private L2 cache comes in at 0.36mm². Given that SiFive promises of similar performance to a Cortex-A72, which in turn would be more than double the performance of an A55, it looks like SiFive's U84 core would be extremely competitive in terms of its PPA.

Related: Qualcomm Invests in RISC-V Startup SiFive

Original Submission

takyon writes:

Intel (INTC) Reportedly Offers Over $2 Billion To Acquire the Fabless Semiconductor SiFive as the Consolidation Trend in the Industry Is Nowhere Close to Slowing Down

[According] to Bloomberg, Intel has reportedly offered over $2 billion to acquire the fabless semiconductor SiFive, a provider of commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.

Should this deal become a reality, it would mark the climax of growing bonhomie between Intel and SiFive. For instance, back in 2018, Intel was one of the participants in the Series C funding round of SiFive. Thereafter, in March 2021, SiFive announced a collaboration with the Intel Foundry Business (IFB) to develop innovative new RISC-V computing platforms.

Of course, unlike legacy Instruction Set Architectures (ISAs), RISC-V's proponents believe that it addresses the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, given that that the ISA is layered, extensible, and flexible. It is hardly surprising, therefore, that some believe RISC-V to be the future.

Bear in mind that SiFive was last valued at $500 million, as per the data available at PitchBook. This means that Intel would be paying a premium of over 300 percent relative to SiFive's 2020 valuation.

Previously: SiFive HiFive Unleashed Not as Open as Previously Thought
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
SiFive to Debut a RISC-V PC for Developers in October
SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs

Original Submission