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posted by Fnord666 on Wednesday July 03 2019, @07:52PM   Printer-friendly
from the moore-of-a-guideline dept.

Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:

Intel's New Chip Wizard Has a Plan to Bring Back the Magic (archive)

In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.

[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.

The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.

Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law

Original Submission

Related Stories

Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed 37 comments

Intel's "Tick-Tock" strategy of micro-architectural changes followed by die shrinks has officially stalled. Although Haswell and Broadwell chips have experienced delays, and Broadwell desktop chips have been overshadowed by Skylake, delays in introducing 10nm process node chips have resulted in Intel's famously optimistic roadmap missing its targets by about a whole year. 10nm Cannonlake chips were set to begin volume production in late 2016, but are now scheduled for the second half of 2017. In its place, a third generation of 14nm chips named "Kaby Lake" will be launched. It is unclear what improvements Kaby Lake will bring over Skylake.

Intel will not be relying on the long-delayed extreme ultraviolet (EUV) lithography to make 10nm chips. The company's revenues for the last quarter were better than expected, despite the decline of the PC market. Intel's CEO revealed the stopgap 14nm generation at the Q2 2015 earnings call:

"The lithography is continuing to get more difficult as you try and scale and the number of multi-pattern steps you have to do is increasing," [Intel CEO Brian Krzanich] said, adding, "This is the longest period of time without a lithography node change."

[...] But Krzanich seemed confident that letting up on the gas, at least for now, is the right move – with the understanding that Intel will aim to get back onto its customary two-year cycle as soon as possible. "Our customers said, 'Look, we really want you to be predictable. That's as important as getting to that leading edge'," Krzanich said during Wednesday's earnings call. "We chose to actually just go ahead and insert – since nothing else had changed – insert this third wave [with Kaby Lake]. When we go from 10-nanometer to 7-nanometer, it will be another set of parameters that we'll reevaluate this."

Intel Roadmap
Year   Old   New
2014   14nm Broadwell   14nm Broadwell
2015   14nm Skylake   14nm Skylake
2016   10nm Cannonlake   14nm Kaby Lake
2017   10nm "Tock"   10nm Cannonlake
2018   N/A   10nm "Tock"

Original Submission

Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization" 31 comments

Intel may finally be abandoning its "Tick-Tock" strategy:

As reported at The Motley Fool, Intel's latest 10-K / annual report filing would seem to suggest that the 'Tick-Tock' strategy of introducing a new lithographic process note in one product cycle (a 'tick') and then an upgraded microarchitecture the next product cycle (a 'tock') is going to fall by the wayside for the next two lithographic nodes at a minimum, to be replaced with a three element cycle known as 'Process-Architecture-Optimization'.

Intel's Tick-Tock strategy has been the bedrock of their microprocessor dominance of the last decade. Throughout the tenure, every other year Intel would upgrade their fabrication plants to be able to produce processors with a smaller feature set, improving die area, power consumption, and slight optimizations of the microarchitecture, and in the years between the upgrades would launch a new set of processors based on a wholly new (sometimes paradigm shifting) microarchitecture for large performance upgrades. However, due to the difficulty of implementing a 'tick', the ever decreasing process node size and complexity therein, as reported previously with 14nm and the introduction of Kaby Lake, Intel's latest filing would suggest that 10nm will follow a similar pattern as 14nm by introducing a third stage to the cadence.

Year Process Name Type
2016 14nm Kaby Lake Optimization
2017 10nm Cannonlake Process
2018 10nm Ice Lake Architecture
2019 10nm Tiger Lake Optimization
2020 7nm ??? Process

This suggests that 10nm "Cannonlake" chips will be released in 2017, followed by a new 10nm architecture in 2018 (tentatively named "Ice Lake"), optimization in 2019 (tentatively named "Tiger Lake"), and 7nm chips in 2020. This year's "optimization" will come in the form of "Kaby Lake", which could end up making underwhelming improvements such as slightly higher clock speeds, due to higher yields of the previously-nameed "Skylake" chips. To be fair, Kaby Lake will supposedly add the following features alongside any CPU performance tweaks:

Kaby Lake will add native USB 3.1 support, whereas Skylake motherboards require a third-party add-on chip in order to provide USB 3.1 ports. It will also feature a new graphics architecture to improve performance in 3D graphics and 4K video playback. Kaby Lake will add native HDCP 2.2 support. Kaby Lake will add full fixed function HEVC Main10/10-bit and VP9 10-bit hardware decoding.

Previously: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed

Original Submission

Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's 15 comments

Intel is talking about improvements it has made to transistor scaling for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.

On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.

Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.

Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Performance 24 comments

The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:

Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.

One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.

Not discussed is how to deal with the heat generated in such a stack.

See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs

Original Submission

Another Step Toward the End of Moore's Law 16 comments

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

Intel Reveals Three New Packaging Technologies for Stitching Multiple Dies Into One Processor 12 comments

Intel will be using a few packaging technologies to connect CPU core "chiplets":

Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies.

[...] Compared to interposers, which can be reticle-sized (832mm2) or even larger, [EMIB (Embedded Multi-die Interconnect Bridge)] is just a small (hence, cheap) piece of silicon. It provides the same bandwidth and energy-per-bit advantages of an interposer compared to standard package traces, which are traditionally used for multi-chip packages (MCPs), such as AMD's Infinity Fabric. (To some extent, because the PCH is a separate die, chiplets have actually been around for a very long time.)

[...] Intel showed off a concept product that contains four Foveros stacks, with each stack having eight small compute chiplets that are connected via TSVs to the base die. (So the role of Foveros there is to connect the chiplets as if it were a monolithic die.) Each Foveros stack is then interconnected via two (Co-)EMIB links with its two adjacent Foveros stacks. Co-EMIB is further used to connect the HBM and transceivers to the compute stacks.

Evidently, the cost of such a product would be enormous, as it essentially contains multiple traditional monolithic-class products in a single package. That's likely why Intel categorized it as a data-centric concept product, aimed mainly at the cloud players that are more than happy to absorb those costs in exchange for the extra performance.

[...] When they are ready, these technologies will provide Intel with powerful capabilities for the heterogeneous and data-centric era. On the client side, the benefits of advanced packaging include smaller package size and lower power consumption (for Lakefield, Intel claims a 10x SoC standby power improvement at 2.6mW). In the data center, advanced packaging will help to build very large and powerful platforms on a single package, with performance, latency, and power characteristics close to what a monolithic die would yield. The yield advantage of small chiplets and the establishment of chipset ecosystem are major drivers, too.

Also at The Register, VentureBeat, Guru3D, and PCWorld.

Related: Intel Core i7-8809G with Radeon Graphics and High Bandwidth Memory: Details Leaked
Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More
Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan

Original Submission

Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021 10 comments

Intel says it was too aggressive pursuing 10nm, will have 7nm chips in 2021

[Intel's CEO Bob] Swan made a public appearance at Fortune's Brainstorm Tech conference in Aspen, Colorado, on Tuesday and explained to the audience in attendance that Intel essentially set the bar too high for itself in pursuing 10nm. More specifically, he pointed to Intel's overly "aggressive goal" of going after a 2.7x transistor density improvement over 14nm.

[...] Needless to say, the 10nm delays have caused Intel to fall well behind that transistor density doubling. Many have proclaimed Moore's Law as dead, but as far as Swan is concerned, Moore's Law is not dead. It apparently just needed to undergo an unexpected surgery.

"The challenges of being late on this latest [10nm] node of Moore's Law was somewhat a function of what we've been able to do in the past, which in essence was define the odds on scaling the infrastructure," Swan explains. Bumping up to a 2.7x scaling factor proved to be "very complicated," more so than Intel anticipated. He also says that Intel erred when it "prioritized performance at a time when predictability was really important."

"The short story is we learned from it, we'll get our 10nm node out this year. Our 7nm node will be out in two years and it will be a 2.0X scaling so back to the historical Moore's Law curve," Swan added.

Also at Fortune and Tom's Hardware.


Original Submission

TSMC Shows Off Gigantic Silicon Interposer 14 comments

TSMC Shows Colossal Interposer, Says Moore's Law Still Alive

In the company's first blog post, TSMC has stated that Moore's Law is still alive and well, despite the zeitgeist of recent times being the reverse. The company also showed a colossal 2500mm2 interposer that includes eight HBM memory chips and two big processors.

Godfrey Cheng, TSMC's new head of global marketing, wrote the blog post. He notes that Moore's Law is not about performance, but about transistor density. While performance traditionally improved by increasing the clock speed and architecture, today it is more often improved by increasing parallelization, and hence requires increases in chip size. This enhances the importance of transistor density because chip cost is directly proportional to its area.

[...] "one possible future of great density improvements is to allow the stacking of multiple layers of transistors in something we call Monolithic 3D Integrated Circuits. You could add a CPU on top of a GPU on top of an AI Edge engine with layers of memory in between. Moore's Law is not dead, there are many different paths to continue to increase density."

[...] [System-technology co-optimization (STCO)] is done through advanced packaging, for which TSMC supports silicon-based interposers and fan-out-based chiplet integration. It also has techniques to stack chips on wafers, or stack wafers on top of other wafers. As one such example, TSMC showed a nearly-2500mm2 silicon interposer – the world's largest – on top of which two 600mm2 processors are placed and eight 75mm2 HBM memory chips, which makes for 1800mm2 of compute and memory silicon on top of the interposer-based package, well over two times the conventional reticle size limit.

Related: Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Performance
Another Step Toward the End of Moore's Law
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan

Original Submission

Intel's Process Nodes Will Trail Behind Competitors Until at Least Late 2021 16 comments

Intel Says Process Tech to Lag Competitors Until Late 2021, Will Regain Lead with 5nm (archive)

It appears that 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday covering a wide range of topics, but noted that despite being "undoubtedly in the 10nm era," the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021. Davis also said that Intel wouldn't regain process leadership until it produces the 5nm node at an unspecified date.

Davis commented that the company was "definitely in the 10nm era" with Ice Lake client chips and networking ASICs already shipping, along with the pending release of discrete GPUs and Ice Lake Xeons. Intel is also moving well along the path of inter-node development, which consists of "+" revisions to existing processes. Davis said the 10nm inter-node step provides a "step-function move" with the Tiger Lake chips based on the 10nm+ process as the company awaits its 7nm process.

However, Davis noted that in spite of the shipping products and pending "+" revisions to the 10nm process, its process node still lags behind competitors, stating:

"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."

Intel Launches Coffee Lake Refresh, Roadmap Leaks Showing No "10nm" Desktop Parts Until 2022
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
Intel Roadmap Shows Plans for "5nm", "3nm", "2nm", and "1.4nm" Process Nodes by 2029

Original Submission

Jim Keller Resigns from Senior Vice President Role at Intel 19 comments

Jim Keller Resigns from Intel, Effective Immediately

Intel has just published a news release on its website stating that Jim Keller has resigned from the company, effective immediately, due to personal reasons. Jim Keller was hired by Intel two years ago to the role as Senior Vice President of Intel's Silicon Engineering Group, after a string of successes at Tesla, AMD, Apple, AMD (again), and PA Semiconductor. As far as we understand, Jim's goal inside Intel was to streamline a lot of the product development process on the silicon side, as well as providing strategic platforms though which future products can be developed and optimized to market. We also believe that Jim Keller has had a hand in looking at Intel's manufacturing processes, as well as a number of future products.

Intel's press release today states that Jim Keller is leaving the position on June 11th due to personal reasons. However, he will remain with the company as a consultant for six months in order to assist with the transition.

[...] Jim Keller's history in the industry has been well documented – his work has had a significant effect in a number of areas that have propelled the industry forward. This includes work on Apple's A4 and A5 processors, AMD's K8 and Zen high-level designs, as well as Tesla's custom silicon for self driving which analysts have Tesla's competitors have said put the company up to seven years ahead.

Jim Keller (engineer).

Also at Reuters, Phoronix, Bloomberg, and Business Insider.

See also: Why Intel is betting its chips on microprocessor mastermind Jim Keller
Exclusive: Internal Memo Shows Murthy’s Remarks Over Jim Keller’s Departure, Details About New Structuring, Raja Koduri To Head Architectural Roadmap

Related: Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan

Original Submission

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  • (Score: 0) by Anonymous Coward on Wednesday July 03 2019, @08:10PM (3 children)

    by Anonymous Coward on Wednesday July 03 2019, @08:10PM (#862881)

    Let's see if it scales to the yields Intel is accustomed to.

    • (Score: 5, Interesting) by takyon on Wednesday July 03 2019, @08:19PM

      by takyon (881) <{takyon} {at} {}> on Wednesday July 03 2019, @08:19PM (#862888) Journal

      They are going to say goodbye to the 28-core monolithic chips and use chiplets like AMD does. That should mitigate some of the yield issues. EUV will also help (Samsung and TSMC are using it now).

      [SIG] 10/28/2017: Soylent Upgrade v14 []
    • (Score: 2) by richtopia on Wednesday July 03 2019, @08:33PM (1 child)

      by richtopia (3160) on Wednesday July 03 2019, @08:33PM (#862898) Homepage Journal

      This might be the big win that Intel is betting on. Intel has some massive capital expenditures now: F42 in AZ is getting tools, Oregon is expanding, plans for greenfield expansion in Ireland, and F11-x in NM is growing. With how slow the 10nm rollout has been it is odd to see this type of investment without a product to manufacture. From the description these technologies don't require new tooling as much as new techniques, so the sites getting built could adapt to the proposed improvements quickly.

      • (Score: 3, Interesting) by takyon on Wednesday July 03 2019, @09:12PM

        by takyon (881) <{takyon} {at} {}> on Wednesday July 03 2019, @09:12PM (#862908) Journal

        I'm not sure I see it as a plan for big winning. More like a plan for keeping up with the rest of the pack.

        TSMC "5nm" [] = 45% area reduction = 1.8x transistor density. Combine that with a "3nm" and maybe smaller nodes, and they should be able to get at least 3x from "pitch scaling", maybe more.

        TSMC's wafer-on-wafer plans [] cover the latter portion of the improvements.

        There are other tricks left in the bag lab that could reduce power consumption, increase frequency, and allow vertical scaling (which probably isn't feasible with how hot chips are running today).

        Intel's Foveros, Big/Small (like ARM's big.LITTLE/DynamIQ), and DRAM stacking/integration plans [] will be more interesting in the long run than some scaling innovations that are going to be industry standard.

        [SIG] 10/28/2017: Soylent Upgrade v14 []
  • (Score: 3, Insightful) by Rupert Pupnick on Wednesday July 03 2019, @08:30PM (2 children)

    by Rupert Pupnick (7277) on Wednesday July 03 2019, @08:30PM (#862893) Journal

    Jim Keller: Chip Wizard. Semiconductor Rock Star. Redefiner of Long Standing Tech Concepts. Oh, excuse me, I mean to say he’s not pedantic about Moore’s Law.

    But at least he’s got a plan as stated right at the end of TFA: make faster computers.

    Are most tech articles on Wired this sensationally dumbed down? Holy crap.

    • (Score: 3, Funny) by takyon on Wednesday July 03 2019, @08:48PM

      by takyon (881) <{takyon} {at} {}> on Wednesday July 03 2019, @08:48PM (#862903) Journal

      Wired's articles are so good, they are hidden behind a paywall. Luckily pierced through.

      [SIG] 10/28/2017: Soylent Upgrade v14 []
    • (Score: 0) by Anonymous Coward on Thursday July 04 2019, @12:08AM

      by Anonymous Coward on Thursday July 04 2019, @12:08AM (#862979)

      Wired has been garbage since the 90s. I'm surprised they are still around.

  • (Score: 1, Insightful) by Anonymous Coward on Wednesday July 03 2019, @09:31PM (4 children)

    by Anonymous Coward on Wednesday July 03 2019, @09:31PM (#862915)

    My guess as to what is going on at intel is they are just hubristically throwing money at a bunch of stuff without a real plan. The accountants/marketers have too much power there so they are falling behind and incapable of collectively dealing with this fact.

    • (Score: 0) by Anonymous Coward on Wednesday July 03 2019, @11:47PM

      by Anonymous Coward on Wednesday July 03 2019, @11:47PM (#862971)

      But let's just redefine Moore's Law!

      Instead of making better chips, we'll just get you to buy twice as many. Bang double the compute power!!

    • (Score: 1, Informative) by Anonymous Coward on Thursday July 04 2019, @12:11AM (1 child)

      by Anonymous Coward on Thursday July 04 2019, @12:11AM (#862980)

      but otherwise correct. In the past the marketers could basically sell the customer whatever they wanted and engineering had to fix it, but Intel cut too many corners on employee bonuses and ensuring any kind of work-life balance between the 1980s and the 2000s, finally culling enough people that the smart and motivated ones left for greener pastures, particularly if they weren't on the management track (there were salary caps on engineers and while you could get bonuses or stock options above that, you had to be considered both a 'real rock star' employee and discreet to get them.)

      Evidence: A relative is worn out husk from working there.

    • (Score: 2) by Rupert Pupnick on Thursday July 04 2019, @12:15AM

      by Rupert Pupnick (7277) on Thursday July 04 2019, @12:15AM (#862983) Journal

      Accountants generally hate spending on R&D.

  • (Score: 0) by Anonymous Coward on Thursday July 04 2019, @12:14AM

    by Anonymous Coward on Thursday July 04 2019, @12:14AM (#862982)

    Intel suxxors.

  • (Score: 0) by Anonymous Coward on Thursday July 04 2019, @06:16AM (1 child)

    by Anonymous Coward on Thursday July 04 2019, @06:16AM (#863045)
    How many years has it taken to double CPU single thread performance? Still seems like we're plateauing on single threaded performance and the rest of the performance increases is on parallel stuff.

    Parallel performance is a far easier problem to solve - make it cheaper, use less power and generate less heat. Then add as many as you can afford. If your computation problems are parallel enough to run on multiple cores they're often parallel enough to run on multiple computers.

    Layering storage circuitry on top of each other makes sense (e.g. in SSDs - only a tiny percentage of the circuitry is active and generating heat at a time). But layering CPU circuitry on top of each other will increase the max heat generation density a lot more. The shortened distances will only help a bit in reducing the heat generated while increasing the difficulty of pumping away the heat. Will it be cheaper once you add all the stuff needed to deal with that?
    • (Score: 3, Interesting) by takyon on Thursday July 04 2019, @08:02AM

      by takyon (881) <{takyon} {at} {}> on Thursday July 04 2019, @08:02AM (#863068) Journal

      Shortening the distance between RAM and CPU [] could reduce some heat and speed up operations massively. Replacing the RAM with universal memory [] would also be a big help. If it can take the heat, stack that onto or inside the CPU.

      Neuromorphic computing will be well suited to scaling vertically since it has inherently low power consumption and works kind of like a brain with not much active at once. But for classical CPUs, it's unclear how heat will be dealt with, although you can see that TSMC is also pursuing Wafer-on-Wafer (WoW). That's at least two companies that think that at least a doubling of density is possible with crude stacking. Beyond that, a new type of transistor [], material, or cooling method could help with the heat problem.

      Intel supposedly has an actual IPC increase coming, 18% with Ice Lake []. Setting aside whether this is valid, wiped out by security mitigations, or paired with lower clock speeds on an immature node, we should be grateful for any gains we get. In other industries, making something 5% better/more efficient would have an impact of billions of dollars. Obviously, a smaller increase won't make you run out and buy it like double performance in a single year would, but incremental gains add up.

      I'm optimistic that we'll see more software exploiting parallelism, now that we are entering an era of ubiquitous 8-cores (counting game consoles and smartphones) and mainstream 16-cores [].

      [SIG] 10/28/2017: Soylent Upgrade v14 []
  • (Score: 0) by Anonymous Coward on Thursday July 04 2019, @07:06AM (1 child)

    by Anonymous Coward on Thursday July 04 2019, @07:06AM (#863052)

    Moore's law is not dead but if you think so you're stupid.

    Good to see Trump's speech writer keeps himself busy when the boss is traveling.