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posted by martyb on Wednesday July 24 2019, @02:33PM   Printer-friendly [Skip to comment(s)]
from the imagine-a-beowolf-cluster-of-these...on-a-chip! dept.

First 3D Nanotube and RRAM ICs Come Out of Foundry

Here's something you don't see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA's Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA's plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world's leading edge foundries.

"This wafer was made just last Friday... and it's the first monolithic 3D IC ever fabricated within a foundry," he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today's 7-nanometer chips. That's especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.

The project is only about a year old, but by the end of its 3.5-year run, DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit.

What Shulaker showed on Tuesday can't do all that yet, of course. But it's a key milestone in that journey. Together with SkyWater Technology Foundry and other partners "we've completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry," he said.

Here's the paper I've linked a dozen times in the last year.


Original Submission

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3DSoC Program Enters Into Second Phase; ARM Announces Three-Year DARPA Partnership 6 comments

DARPA 3DSoC CNFET project moves towards commercialisation phase

Skywater, the US government trusted fab partner, and MIT have announced that the DARPA Three Dimensional Monolithic System-on-a-Chip (3DSoC) programme, has entered its second phase.

After completing the program's initial phase, focused on transferring the Carbon Nanotube Field Effect Transistor (CNFET)-based 3DSoC technology into SkyWater's 200 mm production facility, phase two will focus on refining manufacturing quality, yield, performance, and density – key elements of commercial viability.

[...] A 3DSoC program update will be presented by MIT professor, Dr. Max Shulaker at the virtual 2020 DARPA Electronics Resurgence Initiative (ERI) Summit on August 20th.

Arm Announces Three Year Partnership With DARPA Aimed At Maintaining U.S. Chip Design Lead

In a development that falls in line with recent U.S. efforts to bring semiconductor manufacturing inside its shores, British chip design house Arm announced yesterday that it has entered into a three-year partnership agreement with the Defence Advanced Research Projects Agency (DARPA). The announcement came as the agency wrapped off an event related to its Electronic Resurgence Initiative (ERI), which is focused on reducing reliance on internationally fabricated semiconductors.

Under the partnership, all of Arm's commercial chip design architectures and intellectual property will be available for use on DARPA projects. The duo will also collaborate on efforts such as sensors that rely on low power use for constant monitoring. At the ERI Summit yesterday, Arm's chief executive officer Simon Segars focused his discussion on devices that fall under the ambit of the Internet of Things (IoT), and the connection of these devices with next-generation 5G networks.

Previously: DARPA's 3DSoC Becoming a Reality

Related: Washington in Talks with Chipmakers about Building U.S. Factories


Original Submission

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  • (Score: 1, Insightful) by Anonymous Coward on Wednesday July 24 2019, @02:59PM (7 children)

    by Anonymous Coward on Wednesday July 24 2019, @02:59PM (#870691)

    How do they cool it?

    • (Score: 2) by takyon on Wednesday July 24 2019, @03:05PM (6 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday July 24 2019, @03:05PM (#870695) Journal

      From "3DSoC Target Characteristics":

      Inclusion of > 4GB of non-volatile memory in a monolithic SoC that has a 2D footprint of no more than 200mm2 and dissipates < 500mW of average operating power.

      If power consumption is only 0.5 W maximum, they may not need any cooling at all. While it's "3D", it's far from being a dense stack of thousands of CPU core layers, all operating at once.

      If this technology is scaled up to consume more power for manycores, then we can worry about cooling.

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      • (Score: 5, Funny) by DannyB on Wednesday July 24 2019, @03:19PM

        by DannyB (5839) Subscriber Badge on Wednesday July 24 2019, @03:19PM (#870700) Journal

        Immersion into liquid which can conduct the heat away efficiently.

        Use, say, liquid iron. As long as the chip temperature is higher heat will flow in the correct direction.

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      • (Score: 2) by Alfred on Wednesday July 24 2019, @03:22PM (4 children)

        by Alfred (4006) on Wednesday July 24 2019, @03:22PM (#870703) Journal
        I would expect the CPU layers to generate significantly more heat then the flash layers. I imagine the middle layers will be nice and toasty so cooling could be an issue unless they are going to thermally throttle it. Could work great as long as apple doesn't do the thermal design.

        Like any specs they will be misleading

        transmit 50 terabits per second while consuming less than 2 picojoules per bit.

        What do they mean by transmit? I thought they meant moving data in the chip, maybe thats not it. 50Tbit(10E12)*2pJ(10E-12) = 100 Joules/sec = 100 watts. Just to move data? That seems off. I doubt my desktop CPU, without the advantage of on die communication, uses that much to talk to RAM. So how much more when we add CPU consumption? Maybe they are looking to that as a burst rate and not continuous.

        Either way, specs are misleading

        • (Score: 2) by takyon on Wednesday July 24 2019, @03:31PM (3 children)

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday July 24 2019, @03:31PM (#870707) Journal

          That refers to memory bandwidth between the CPU and integrated DRAM. See page 5:

          Memory Access Parameter / 2D / 3D TSV Package / 3DSoC
          Total I/O / 512 / 1K / 33K
          Max Bandwidth (Gb/s) / 400 / 1K / 46K
          Memory access energy (pJ/bit) / 52 / 32 / 1.5
          VDD (Volts System) / 1.6 / 1.2 / 0.6

          46K Gb/s = 46 terabits per second

          The advantage here is that by shortening the distance data has to travel from the CPU to the DRAM, you can get incredible performance increases and reduce the energy needed.

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          • (Score: 2) by Alfred on Wednesday July 24 2019, @08:08PM (2 children)

            by Alfred (4006) on Wednesday July 24 2019, @08:08PM (#870839) Journal
            Right. Crazy good transfer speeds. But unless I got my math wrong, 100W is a lot for that.
            • (Score: 2) by takyon on Wednesday July 24 2019, @08:47PM

              by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday July 24 2019, @08:47PM (#870864) Journal

              They say that it "dissipates < 500mW of average operating power" so that's what I'm going to go with.

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            • (Score: 2) by sgleysti on Thursday July 25 2019, @12:07AM

              by sgleysti (56) on Thursday July 25 2019, @12:07AM (#870904)

              Since they call the 2pJ/bit metric "memory access energy", I'm guessing this is the energy to read one bit of the nonvolatile memory. Since this is specified at 4GB = 32Gb, it would take 2pJ/bit * 32Gb = 64mJ to read the entire memory on the chip once.

              If that's all that metric means, it is orthogonal to the power required for the 50Tb/s transmission bandwidth, and the summary is just confusing. This is my best guess.

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