from the imagine-a-beowolf-cluster-of-these...on-a-chip! dept.
Here's something you don't see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA's Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA's plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world's leading edge foundries.
"This wafer was made just last Friday... and it's the first monolithic 3D IC ever fabricated within a foundry," he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today's 7-nanometer chips. That's especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.
The project is only about a year old, but by the end of its 3.5-year run, DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit.
What Shulaker showed on Tuesday can't do all that yet, of course. But it's a key milestone in that journey. Together with SkyWater Technology Foundry and other partners "we've completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry," he said.
Here's the paper I've linked a dozen times in the last year.
Skywater, the US government trusted fab partner, and MIT have announced that the DARPA Three Dimensional Monolithic System-on-a-Chip (3DSoC) programme, has entered its second phase.
After completing the program's initial phase, focused on transferring the Carbon Nanotube Field Effect Transistor (CNFET)-based 3DSoC technology into SkyWater's 200 mm production facility, phase two will focus on refining manufacturing quality, yield, performance, and density – key elements of commercial viability.
[...] A 3DSoC program update will be presented by MIT professor, Dr. Max Shulaker at the virtual 2020 DARPA Electronics Resurgence Initiative (ERI) Summit on August 20th.
In a development that falls in line with recent U.S. efforts to bring semiconductor manufacturing inside its shores, British chip design house Arm announced yesterday that it has entered into a three-year partnership agreement with the Defence Advanced Research Projects Agency (DARPA). The announcement came as the agency wrapped off an event related to its Electronic Resurgence Initiative (ERI), which is focused on reducing reliance on internationally fabricated semiconductors.
Under the partnership, all of Arm's commercial chip design architectures and intellectual property will be available for use on DARPA projects. The duo will also collaborate on efforts such as sensors that rely on low power use for constant monitoring. At the ERI Summit yesterday, Arm's chief executive officer Simon Segars focused his discussion on devices that fall under the ambit of the Internet of Things (IoT), and the connection of these devices with next-generation 5G networks.
Previously: DARPA's 3DSoC Becoming a Reality