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takyon writes:

JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard.

[...] JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 24 GB per stack.

This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updates the MISR polynomial options for these new configurations.

Some existing High Bandwidth Memory products already had a per pin bandwidth of 2.4 Gbps. However, the increase in stack size and density could allow a product with 96 GB of DRAM using just four stacks (16 Gb DRAM × 12 × 4), up from 32 GB (8 Gb DRAM × 8 × 4).

This update apparently applies to HBM2 and is not considered a third or fourth generation of HBM.

Also at Wccftech and AnandTech.

Previously: Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks

Original Submission

takyon writes:

Samsung HBM2E 'Flashbolt' Memory for GPUs: 16 GB Per Stack, 3.2 Gbps

Samsung has introduced the industry's first memory that correspond to the HBM2E specification. The company's new Flashbolt memory stacks increase performance by 33% and offer double per-die as well as double per-package capacity. Samsung introduced its HBM2E DRAMs at GTC, indicating that the gaming market is a target market for this memory.

Samsung's Flashbolt KGSDs (known good stacked die) are based on eight 16-Gb memory dies interconnected using TSVs (through silicon vias) in an 8-Hi stack configuration. Every Flashbolt package features a 1024-bit bus with a 3.2 Gbps data transfer speed per pin, thus offering up to 410 GB/s of bandwidth per KGSD.

Samsung positions its Flashbolt KGSDs for next-gen datacenter, HPC, AI/ML, and graphics applications. By using four Flashbolt stacks with a processor featuring a 4096-bit memory interface, developers can get 64 GB of memory with a 1.64 TB/s peak bandwidth, something that will be a great advantage for capacity and bandwidth-hungry chips. With two KGSDs they get 32 GB of DRAM with an 820 GB/s peak bandwidth.

Also at Tom's Hardware.

Previously: Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks
JEDEC Updates High Bandwidth Memory Standard With New 12-Hi Stacks

Original Submission

takyon writes:

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.

The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.

GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.

2.5D/3D packaging.

Related: Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages
SK Hynix Announces HBM2E Memory for 2020 Release
GlobalFoundries Develops "12LP+" Fabrication Process
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture

Original Submission

takyon writes:

SK Hynix has licensed technology that could enable the production of 16-layer High Bandwidth Memory (HBM) stacks. Bandwidth could also be increased by a superior interconnect density:

SK Hynix has inked a new broad patent and technology licensing agreement with Xperi Corp. Among other things, the company licensed the DBI Ultra 2.5D/3D interconnect technology developed by Invensas. The latter was designed to enable building up to 16-Hi chip assemblies, including next-generation memory, and highly-integrated SoCs that feature numerous homogeneous layers.

Invensas' DBI Ultra is a proprietary die-to-wafer hybrid bonding interconnect technology that supports from 100,000 to 1,000,000 interconnects per mm², using interconnect pitches as small as 1 µm. According to the company, the much greater number of interconnects can offer dramatically increased bandwidth vs. conventional copper pillar interconnect technology, which only goes as high as 625 interconnects per mm². The small interconnects also offer a shorter z-height, making it possible to build a stacked chip with 16 layers in the same space as conventional 8-Hi chips, allowing for greater memory densities.

12-Hi stacks have been specified, but have only recently reached development/production.

JEDEC (Joint Electron Device Engineering Council) has updated the HBM2 standard to accommodate 3.2Gbps/pin speeds. This is in line with Samsung's "Flashbolt" HBM2E memory (although SK Hynix and Samsung may push speeds to a further 3.6Gbps or 4.2Gbps/pin), which will enter into mass production soon. JEDEC has not adopted the "HBM2E" nomenclature used by Samsung, SK Hynix, and others.

Micron has announced that it is shipping LPDDR5 DRAM to customers. LPDDR5 will be used in the Xiaomi Mi 10, ZTE Axon 10s Pro 5G, and Samsung Galaxy S20 (yes, even 16 GB of it).

Original Submission