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posted by martyb on Thursday September 26 2019, @09:22PM   Printer-friendly
from the not-dead-yet dept.

https://www.anandtech.com/show/14905/globalfoundries-unveils-12lp-technology-massive-performance-power-improvements

GlobalFoundries has introduced its 12LP+ fabrication process that relies on the groundwork set by its 14LPP and 12LP technologies and provides significant improvements when it comes to performance, power, and area (PPA) scaling. The specialty foundry positions the technology for developers of chips for cloud and edge AI applications.

GlobalFoundries' 12LP+ manufacturing technology builds upon the company's 12LP process yet enables a 20% increase in performance (at the same power and complexity) or a 40% reduction in power requirements (at the same clocks and complexity) as well as a 15% improvement in logic area scaling when compared to 12LP platform. Among other things, 12LP+ supports 0.5V SRAM bit cells (which probably use IP that the company designed for its 7 nm nodes). In addition, GF developed a new 2.5D interposer that enables 12LP+ SoCs to work with HBM memory.

So, "LP" is Low-Power, and "LPP" is Low-Power Plus", and "LP+" is Low-Power Plus", too?


Original Submission

Related Stories

GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.

The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.

GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.

2.5D/3D packaging.

Related: Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages
SK Hynix Announces HBM2E Memory for 2020 Release
GlobalFoundries Develops "12LP+" Fabrication Process
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture


Original Submission

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  • (Score: 0) by Anonymous Coward on Thursday September 26 2019, @09:53PM

    by Anonymous Coward on Thursday September 26 2019, @09:53PM (#899315)

    78 rpm - tinny chipmonks
    45 rpm - teenybopper attention span
    33 1/3 rpm - (lp) long playing, last long time

  • (Score: 0) by Anonymous Coward on Thursday September 26 2019, @09:58PM

    by Anonymous Coward on Thursday September 26 2019, @09:58PM (#899318)

    So, "LP" is Low-Power, and "LPP" is Low-Power Plus", and "LP+" is Low-Power Plus", too?

    "LP+" means "Low-Plus Power".

  • (Score: 0) by Anonymous Coward on Thursday September 26 2019, @11:05PM (1 child)

    by Anonymous Coward on Thursday September 26 2019, @11:05PM (#899336)

    Or is it just populated with marketing idiots now?

    • (Score: 0) by Anonymous Coward on Thursday September 26 2019, @11:57PM

      by Anonymous Coward on Thursday September 26 2019, @11:57PM (#899347)

      What exactly do you think is wrong with their announcement?

  • (Score: 2) by maxwell demon on Friday September 27 2019, @07:59PM

    by maxwell demon (1608) on Friday September 27 2019, @07:59PM (#899689) Journal

    So low-power plus means it consumes more power than low-power? (plus = more)

    --
    The Tao of math: The numbers you can count are not the real numbers.
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