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posted by martyb on Wednesday November 06 2019, @06:00PM   Printer-friendly [Skip to comment(s)]
from the hang^W-stack-'em-high! dept.

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.

The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.

GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.

2.5D/3D packaging.

Related: Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages
SK Hynix Announces HBM2E Memory for 2020 Release
GlobalFoundries Develops "12LP+" Fabrication Process
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture


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Related Stories

Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages 7 comments

Samsung HBM2E 'Flashbolt' Memory for GPUs: 16 GB Per Stack, 3.2 Gbps

Samsung has introduced the industry's first memory that correspond to the HBM2E specification. The company's new Flashbolt memory stacks increase performance by 33% and offer double per-die as well as double per-package capacity. Samsung introduced its HBM2E DRAMs at GTC, indicating that the gaming market is a target market for this memory.

Samsung's Flashbolt KGSDs (known good stacked die) are based on eight 16-Gb memory dies interconnected using TSVs (through silicon vias) in an 8-Hi stack configuration. Every Flashbolt package features a 1024-bit bus with a 3.2 Gbps data transfer speed per pin, thus offering up to 410 GB/s of bandwidth per KGSD.

Samsung positions its Flashbolt KGSDs for next-gen datacenter, HPC, AI/ML, and graphics applications. By using four Flashbolt stacks with a processor featuring a 4096-bit memory interface, developers can get 64 GB of memory with a 1.64 TB/s peak bandwidth, something that will be a great advantage for capacity and bandwidth-hungry chips. With two KGSDs they get 32 GB of DRAM with an 820 GB/s peak bandwidth.

Also at Tom's Hardware.

Previously: Samsung Increases Production of 8 GB High Bandwidth Memory 2.0 Stacks
JEDEC Updates High Bandwidth Memory Standard With New 12-Hi Stacks


Original Submission

SK Hynix Announces HBM2E Memory for 2020 Release 2 comments

[HBM is High Bandwidth Memory. -Ed.]

SK Hynix Announces 3.6 Gbps HBM2E Memory For 2020: 1.8 TB/sec For Next-Gen Accelerators

SK Hynix this morning has thrown their hat into the ring as the second company to announce memory based on the HBM2E standard. While the company isn't using any kind of flash name for the memory (ala Samsung's Flashbolt), the idea is the same: releasing faster and higher density HBM2 memory for the next generation of high-end processors. Hynix's HBM2E memory will reach up to 3.6 Gbps, which as things currently stand, will make it the fastest HBM2E memory on the market when it ships in 2020.

As a quick refresher, HBM2E is a small update to the HBM2 standard to improve its performance, serving as a mid-generational kicker of sorts to allow for higher clockspeeds, higher densities (up to 24GB with 12 layers), and the underlying changes that are required to make those happen. Samsung was the first memory vendor to announce HBM2E memory earlier this year, with their 16GB/stack Flashbolt memory, which runs at up to 3.2 Gbps. At the time, Samsung did not announce a release date, and to the best of our knowledge, mass production still hasn't begun.

[...] [SK Hynix's] capacity is doubling, from 8 Gb/layer to 16 Gb/layer, allowing a full 8-Hi stack to reach a total of 16GB. It's worth noting that the revised HBM2 standard actually allows for 12-Hi stacks, for a total of 24GB/stack, however we've yet to see anyone announce memory quite that dense.

See also: HBM2E: The E Stands For Evolutionary

Previously: JEDEC Updates High Bandwidth Memory Standard With New 12-Hi Stacks
Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages


Original Submission

GlobalFoundries Develops "12LP+" Fabrication Process 5 comments

https://www.anandtech.com/show/14905/globalfoundries-unveils-12lp-technology-massive-performance-power-improvements

GlobalFoundries has introduced its 12LP+ fabrication process that relies on the groundwork set by its 14LPP and 12LP technologies and provides significant improvements when it comes to performance, power, and area (PPA) scaling. The specialty foundry positions the technology for developers of chips for cloud and edge AI applications.

GlobalFoundries' 12LP+ manufacturing technology builds upon the company's 12LP process yet enables a 20% increase in performance (at the same power and complexity) or a 40% reduction in power requirements (at the same clocks and complexity) as well as a 15% improvement in logic area scaling when compared to 12LP platform. Among other things, 12LP+ supports 0.5V SRAM bit cells (which probably use IP that the company designed for its 7 nm nodes). In addition, GF developed a new 2.5D interposer that enables 12LP+ SoCs to work with HBM memory.

So, "LP" is Low-Power, and "LPP" is Low-Power Plus", and "LP+" is Low-Power Plus", too?


Original Submission

SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture 13 comments

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year's we've seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we've seen a lot of vendors make the switch from licensing Arm's architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on the ISA. While many vendors do choose to design their own microarchitectures to replace Arm-based microcontroller designs in their products, things get a little bit more complicated once you scale up in performance. It's here where SiFive comes into play as a RISC-V IP vendor offering more complex designs for companies to license – essentially a similar business model to Arm's – just that it's based on the new open ISA.

Today's announcement marks a milestone in SiFive's IP offering as the company is revealing its first ever out-of-order CPU microarchitecture, promising a significant performance jump over existing RISC-V cores, and offering competitive PPA metrics compared to Arm's products. [...] SiFive's design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. The A72 is quite an old comparison point by now, however SiFive's PPA targets are comparatively quite high, meaning the U8 should be quite competitive to Arm's latest generation cores.

Performance gains over previous designs are substantial:

The performance increases compared to previous generation SiFive cores are extremely impressive: Against a U54 at ISO-process, the new U84 features a 5.3x performance increase in SPECint2006. When taking into account the process node improvements that allow the U84 to clock higher, the generational increases that we'd be seeing in products will be more akin to a factor of 7.2x.

In terms of PPA, compared to a U7-series CPU, IPC increases come in at 2.3x resulting in 3.1x higher performance (ISO-process). A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.

On the same 7nm process, the U84 lands in at 0.28mm² per core and a cluster comprising four cores and a 2MB L2 cache measure in at 2.63mm². For comparison, an Arm Cortex-A55 as measured on the Kirin 980, also on 7nm, a core with its 128KB private L2 cache comes in at 0.36mm². Given that SiFive promises of similar performance to a Cortex-A72, which in turn would be more than double the performance of an A55, it looks like SiFive's U84 core would be extremely competitive in terms of its PPA.

Related: Qualcomm Invests in RISC-V Startup SiFive


Original Submission

SiFive to Debut a RISC-V PC for Developers in October 9 comments

SiFive to Debut RISC-V PC for Developers based on Freedom U740 next-gen SoC

In recent years, people have discussed the need to have Arm-based PCs or workstations for developers to work directly on the target hardware, and there are now several options including SynQuacer E-Series 24-Core Arm PC, Ampere eMAG 64bit Arm Workstation, and HoneyComb LX2K 16-core Arm Workstation.

Now it appears we'll soon get something similar for RISC-V architecture with SiFive to debut the first RISC-V PC for developers at the Linley Fall Processor Conference 2020 taking place on October 20-22 and October 27-29. The PC will be powered by Freedom U740 next-generation RISC-V processor that will also be introduced at the event.

We have very few details about this point in time, but the company points the SiFive Freedom U740 (FU740) SoC will enable professional developers to create RISC-V applications from bare-metal to Linux-based. The processor is said to combines[sic] a heterogeneous mix+match core complex with modern PC expansion capabilities, which probably means PCIe, SATA etc.., and the company will provide tools to ease professional software development.

Freedom U740 details are unknown, but Freedom U540 is a quad-core CPU that was used in the HiFive Unleashed single-board computer.

Related: SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)


Original Submission

Intel May Attempt to Acquire SiFive for $2 Billion 8 comments

Intel (INTC) Reportedly Offers Over $2 Billion To Acquire the Fabless Semiconductor SiFive as the Consolidation Trend in the Industry Is Nowhere Close to Slowing Down

[According] to Bloomberg, Intel has reportedly offered over $2 billion to acquire the fabless semiconductor SiFive, a provider of commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.

Should this deal become a reality, it would mark the climax of growing bonhomie between Intel and SiFive. For instance, back in 2018, Intel was one of the participants in the Series C funding round of SiFive. Thereafter, in March 2021, SiFive announced a collaboration with the Intel Foundry Business (IFB) to develop innovative new RISC-V computing platforms.

Of course, unlike legacy Instruction Set Architectures (ISAs), RISC-V's proponents believe that it addresses the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, given that that the ISA is layered, extensible, and flexible. It is hardly surprising, therefore, that some believe RISC-V to be the future.

Bear in mind that SiFive was last valued at $500 million, as per the data available at PitchBook. This means that Intel would be paying a premium of over 300 percent relative to SiFive's 2020 valuation.

Previously: SiFive HiFive Unleashed Not as Open as Previously Thought
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
SiFive to Debut a RISC-V PC for Developers in October
SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs


Original Submission

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