from the small-roads-on-that-map dept.
One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn't expect to see disclosed was an extended roadmap of Intel's upcoming manufacturing processes.
[...] Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then 5nm in 2023, 3nm in 2025, 2nm in 2027, and 1.4 nm in 2029. This is the first mention on 1.4nm for Intel on any slide, so this confirms where Intel is going, and just for context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.
It is perhaps worth noting that some of the talks at this year's IEDM features dimensions on the order of 0.3nm with what are called '2D self-assembly' materials, so something this low isn't unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.
Inbetween each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.
The interesting element to this slide is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older '++' version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.
It appears that 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday covering a wide range of topics, but noted that despite being "undoubtedly in the 10nm era," the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021. Davis also said that Intel wouldn't regain process leadership until it produces the 5nm node at an unspecified date.
Davis commented that the company was "definitely in the 10nm era" with Ice Lake client chips and networking ASICs already shipping, along with the pending release of discrete GPUs and Ice Lake Xeons. Intel is also moving well along the path of inter-node development, which consists of "+" revisions to existing processes. Davis said the 10nm inter-node step provides a "step-function move" with the Tiger Lake chips based on the 10nm+ process as the company awaits its 7nm process.
However, Davis noted that in spite of the shipping products and pending "+" revisions to the 10nm process, its process node still lags behind competitors, stating:
"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."
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