from the shrinking-lead dept.
It appears that 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday covering a wide range of topics, but noted that despite being "undoubtedly in the 10nm era," the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021. Davis also said that Intel wouldn't regain process leadership until it produces the 5nm node at an unspecified date.
Davis commented that the company was "definitely in the 10nm era" with Ice Lake client chips and networking ASICs already shipping, along with the pending release of discrete GPUs and Ice Lake Xeons. Intel is also moving well along the path of inter-node development, which consists of "+" revisions to existing processes. Davis said the 10nm inter-node step provides a "step-function move" with the Tiger Lake chips based on the 10nm+ process as the company awaits its 7nm process.
However, Davis noted that in spite of the shipping products and pending "+" revisions to the 10nm process, its process node still lags behind competitors, stating:
"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."
Intel Launches Coffee Lake Refresh, Roadmap Leaks Showing No "10nm" Desktop Parts Until 2022
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
Intel Roadmap Shows Plans for "5nm", "3nm", "2nm", and "1.4nm" Process Nodes by 2029
Dubbed 'Coffee Lake Refresh', the 9th generation of Intel's Core CPU product line is a direct refresh of its 8th generation Coffee Lake hardware, with minor enhancements such as a better thermal interface on the high end processors, support for up to 8 cores, and newer chipsets with integrated USB 3.1 Gen2 (10Gbps) and CNVi-enabled Wi-Fi. The hardware is still fundamentally the original 6th Gen Skylake microarchitecture underneath, from 2016, but built on Intel's latest 14nm process variant, in order to extract additional frequency and efficiency, and with more cores at the high-end.
Intel may continue to be largely stuck on a "14nm" process for years to come:
The latest roadmaps come from Tweakers and detail both the Client Commercial CPU products and the Client Mobile CPU products which would be introduced in the future. The authenticity of these roadmaps cannot be confirmed but they are referenced back to the Intel's SIP program and DELL so there might be some legitimacy to them.
[...] It looks like Intel will stick with 14nm++ for a while as the roadmap reveals. Around Q2 2020, Intel will launch their Comet Lake-S processors, featuring up to 10 core SKUs. These would be followed by Intel's Rocket Lake-S parts which would also be based on an optimized 14nm process node. It looks like we can expect a 10nm or sub-10nm part from Intel only around 2022 which is about the same time Intel is expected to launch their Ocean Cove CPU architecture.
Ocean Cove is a future chip architecture under development at Intel which will launch after Golden Cove (2021), the successor to Willow Cove (2020) which itself is the successor to Intel's Sunny Cove (Ice Lake) core's architecture.
The roadmap shows Intel using "10nm" sooner for some mobility (laptop) CPUs.
Intel's Senior Vice President Jim Keller (who previously helped to design AMD's K8 and Zen microarchitectures) gave a talk at the Silicon 100 Summit that promised continued pursuit of transistor scaling gains, including a roughly 50x increase in gate density:
In 2016, a biennial report that had long served as an industry-wide pledge to sustain Moore's law gave up and switched to other ways of defining progress. Analysts and media—even some semiconductor CEOs—have written Moore's law's obituary in countless ways. Keller doesn't agree. "The working title for this talk was 'Moore's law is not dead but if you think so you're stupid,'" he said Sunday. He asserted that Intel can keep it going and supply tech companies ever more computing power. His argument rests in part on redefining Moore's law.
[...] Keller also said that Intel would need to try other tactics, such as building vertically, layering transistors or chips on top of each other. He claimed this approach will keep power consumption down by shortening the distance between different parts of a chip. Keller said that using nanowires and stacking his team had mapped a path to packing transistors 50 times more densely than possible with Intel's 10 nanometer generation of technology. "That's basically already working," he said.
The ~50x gate density claim combines ~3x density from additional pitch scaling (from "10nm"), ~2x from nanowires, another ~2x from stacked nanowires, ~2x from wafer-to-wafer stacking, and ~2x from die-to-wafer stacking.
Related: Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed
Intel's "Tick-Tock" is Now More Like "Process-Architecture-Optimization"
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Another Step Toward the End of Moore's Law
One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn't expect to see disclosed was an extended roadmap of Intel's upcoming manufacturing processes.
[...] Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then 5nm in 2023, 3nm in 2025, 2nm in 2027, and 1.4 nm in 2029. This is the first mention on 1.4nm for Intel on any slide, so this confirms where Intel is going, and just for context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.
It is perhaps worth noting that some of the talks at this year's IEDM features dimensions on the order of 0.3nm with what are called '2D self-assembly' materials, so something this low isn't unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.
Inbetween each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.
The interesting element to this slide is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older '++' version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.
In a blunt video posted late Thursday evening, outspoken former Intel principal engineer Francois Pidnoel offered his advice on how to "fix" Intel CPUs, criticized current leadership for not being engineers, said AVX512 was a misadventure, and declared that it's only luck AMD hasn't grabbed more market share.
"First, Intel is really out of focus," Piednoel said in the nearly hour-long video presentation. "The leaders of Intel today are not engineers, they are not people who understand what to design to the market."
[...] Pidnoel flat-out dismissed including AVX512 in consumer chips as a mistake. "You had Skylake and Skylake X for a reason," Piednoel said. "AVX512 is designed for a race of throughput that is lost to the GPU already. There's two ways to get throughput. One is to get the throughput is by having larger vectors to your core, and the other way is to have more cores."
[...] "Intel is very lucky AMD cannot get the volume, to be able to compete," Piednoel. "If they were getting volume, the price difference would definitely cost Intel market share a lot more than what they are losing right now."
Related: AVX-512: A "Hidden Gem"?
Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021
Intel's Process Nodes Will Trail Behind Competitors Until at Least Late 2021
Linus Torvalds: Don't Hide Rust in Linux Kernel; Death to AVX-512
Intel Engineering Chief Out After 7nm Product Delays
Intel Faces Class-Action Lawsuit Over "7nm" Delays