TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles
TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they've announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.
Overall, the proposed 1,700 mm² interposer is twice the size of TSMC's 858 mm² reticle limit. Of course, TSMC can't actually produce a single interposer this large all in one shot – that's what the reticle limit is all about – so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.
The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC's EUV-based 5 nm (N5) process technology. This system-in-package product features 'multiple' SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom's press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung's latest HBM2E chips can offer.
Also at Guru3D.
Previously: TSMC Shows Off Gigantic Silicon Interposer
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TSMC Shows Colossal Interposer, Says Moore's Law Still Alive
In the company's first blog post, TSMC has stated that Moore's Law is still alive and well, despite the zeitgeist of recent times being the reverse. The company also showed a colossal 2500mm2 interposer that includes eight HBM memory chips and two big processors.
Godfrey Cheng, TSMC's new head of global marketing, wrote the blog post. He notes that Moore's Law is not about performance, but about transistor density. While performance traditionally improved by increasing the clock speed and architecture, today it is more often improved by increasing parallelization, and hence requires increases in chip size. This enhances the importance of transistor density because chip cost is directly proportional to its area.
[...] "one possible future of great density improvements is to allow the stacking of multiple layers of transistors in something we call Monolithic 3D Integrated Circuits. You could add a CPU on top of a GPU on top of an AI Edge engine with layers of memory in between. Moore's Law is not dead, there are many different paths to continue to increase density."
[...] [System-technology co-optimization (STCO)] is done through advanced packaging, for which TSMC supports silicon-based interposers and fan-out-based chiplet integration. It also has techniques to stack chips on wafers, or stack wafers on top of other wafers. As one such example, TSMC showed a nearly-2500mm2 silicon interposer – the world's largest – on top of which two 600mm2 processors are placed and eight 75mm2 HBM memory chips, which makes for 1800mm2 of compute and memory silicon on top of the interposer-based package, well over two times the conventional reticle size limit.
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TSMC Has Started The Development of The 2nm Lithography Process
Earlier this month, we saw that TSMC was getting its CoWoS interposer and 5nm production lines at full capacity. Yesterday, we found out that AMD and Nvidia bought up all of their excess capacity for next-generation GPU and CPU development. They have also been making advancements in 3nm process development, but have not been able to put much work in because many of the tools necessary are currently unavailable or hard to find due to the COVID-19 pandemic. 3nm is already a lot of work as it is, but in a recent shareholders meeting, DigiTimes was able to figure out that TSMC is already planning to start the development of the 2nm Lithographic process.
TSMC's "3nm" node has reportedly been delayed by 6 months due to the pandemic. Samsung is facing similar delays on their own "3nm" node.
TSMC's "5nm" production has not been delayed, and AMD will reportedly use an exclusive enhanced "5nm" node for Zen 4 CPUs in 2021.
Previously: TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
High Demand Reported for TSMC's Chip-on-Wafer-on-Substrate Packaging
Report: TSMC CoWoS Production Line at Full Capacity as Demand Increases
Despite the downturn of events around the world, TSMC is witnessing a significant increase in demand for its Chip-on-Wafer-on-Substrate (CoWoS) packaging, according to DigiTimes' unnamed industry sources. The Taiwanese silicon manufacturer is purportedly running its CoWoS production lines at full capacity.
CoWoS as is a 2.5D method of packaging multiple individual dies side-by-side on a single silicon interposer. The benefits are the ability to increase the density in small devices as you run into the limits of how big individual dies can be produced, better interconnectivity between dies and lower power consumption.
According to DigiTimes, AMD, Nvidia, HiSilicon, Xilinx and Broadcom have placed orders for the tech, with demand for high-performance computing chips, high bandwidth memory (HBM)-powered AI accelerators and ASICs during the past two weeks.
Examples of CoWoS packaged silicon are [...] AMD's Vega VII graphics cards, as well as Nvidia's V100 cards, which have HBM on the same silicon interposer where the GPU is. With the GPU and memory so close together, memory bandwidth is significantly higher on these chips compared to those using GDDR6 memory located elsewhere on the graphics card's PCB. Additionally, the PCB becomes much smaller.
Also at Wccftech.
Previously: TSMC Shows Off Gigantic Silicon Interposer
TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
(Score: 0) by Anonymous Coward on Friday March 06 2020, @03:49AM
damn thats a big 'micro'chip.