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posted by chromas on Friday April 03 2020, @11:10PM   Printer-friendly
from the gimme-some-o'-that dept.

SK Hynix: Up to DDR5-8400 at 1.1 Volts

Back in November last year, we reported that SK Hynix had developed and deployed its first DDR5 DRAM. Fast forward to the present, and we also know SK Hynix has recently been working on its DDR5-6400 DRAM, but today the company has showcased that it has plans to offer up to DDR5-8400, with on-die ECC, and an operating voltage of just 1.1 Volts.

WIth CPU core counts rising with the fierce battle ongoing between Intel and AMD in the desktop, professional, and now mobile markets, the demand to increase throughput performance is high on the agenda. Memory bandwidth by comparison has not been increasing as much, and at some level the beast needs to be fed. Announcing more technical details on its official website, SK Hynix has been working diligently on perfecting its DDR5 chips with capacity for up to 64 Gb per chip.

Micron will begin selling High Bandwidth Memory (HBM) this year, entering the market alongside Samsung and SK Hynix and potentially lowering prices:

Bundled in their latest earnings call, Micron has revealed that later this year the company will finally introduce its first HBM DRAM for bandwidth-hungry applications. The move will enable the company to address the market for high-bandwidth devices such as flagship GPUs and network processors, which in the last five years have turned to HBM to meet their ever-growing bandwidth needs. And as the third and final of the "big three" memory manufacturers to enter the HBM market, this means that HBM2 memory will finally be available from all three companies, introducing a new wrinkle of competition into that market.

Also at Wccftech.

See also: Cadence DDR5 Update: Launching at 4800 MT/s, Over 12 DDR5 SoCs in Development


Original Submission

Related Stories

JEDEC Releases DDR5 Memory Specification 11 comments

DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond

We'll start with a brief look at capacity and density, as this is the most-straightforward change to the standard compared to DDR4. Designed to span several years (if not longer), DDR5 will allow for individual memory chips up to 64Gbit in density, which is 4x higher than DDR4's 16Gbit density maximum. Combined with die stacking, which allows for up to 8 dies to be stacked as a single chip, then a 40 element LRDIMM can reach an effective memory capacity of 2TB. Or for the more humble unbuffered DIMM, this would mean we'll eventually see DIMM capacities reach 128GB for your typical dual rank configuration.

[...] For DDR5, JEDEC is looking to start things off much more aggressively than usual for a DDR memory specification. Typically a new standard picks up from where the last one started off, such as with the DDR3 to DDR4 transition, where DDR3 officially stopped at 1.6Gbps and DDR4 started from there. However for DDR5 JEDEC is aiming much higher, with the group expecting to launch at 4.8Gbps, some 50% faster than the official 3.2Gbps max speed of DDR4. And in the years afterwards, the current version of the specification allows for data rates up to 6.4Gbps, doubling the official peak of DDR4.

Of course, sly enthusiasts will note that DDR4 already goes above the official maximum of 3.2Gbps (sometimes well above), and it's likely that DDR5 will eventually go a similar route. The underlying goal, regardless of specific figures, is to double the amount of bandwidth available today from a single DIMM. So don't be too surprised if SK Hynix indeed hits their goal of DDR5-8400 later this decade.

[...] JEDEC is also using the introduction of the DDR5 memory standard to make a fairly important change to how voltage regulation works for DIMMs. In short, voltage regulation is being moved from the motherboard to the individual DIMM, leaving DIMMs responsible for their own voltage regulation needs. This means that DIMMs will now include an integrated voltage regulator, and this goes for everything from UDIMMs to LRDIMMs.

JEDEC is dubbing this "pay as you go" voltage regulation, and is aiming to improve/simplify a few different aspects of DDR5 with it. The most significant change is that by moving voltage regulation on to the DIMMs themselves, voltage regulation is no longer the responsibility of the motherboard. Motherboards in turn will no longer need to be built for the worst-case scenario – such as driving 16 massive LRDIMMs – simplifying motherboard design and reining in costs to a degree. Of course, the flip side of this argument is that it moves those costs over to the DIMM itself, but then system builders are at least only having to buy as much voltage regulation hardware as they have DIMMs, and hence the PAYGO philosophy.

"On-die ECC" is mentioned in the press release and slides. If you can figure out what that means, let us know.

See also: Micron Drives DDR5 Memory Adoption with Technology Enablement Program

Previously: DDR5 Standard to be Finalized by JEDEC in 2018
DDR5-4400 Test Chip Demonstrated
Cadence and Micron Plan Production of 16 Gb DDR5 Chips in 2019
SK Hynix Announces Plans for DDR5-8400 Memory, and More


Original Submission

SK Hynix Ready to Ship 16 Gb DDR5 Dies, Has Its Own 64 GB DDR5-4800 Modules 7 comments

DDR5 is Coming: First 64GB DDR5-4800 Modules from SK Hynix

DDR5 is the next stage of platform memory for use in the majority of major compute platforms. The specification (as released in July 2020) brings the main voltage down from 1.2 V to 1.1 V, increases the maximum silicon die density by a factor 4, doubles the maximum data rate, doubles the burst length, and doubles the number of bank groups. Simply put, the JEDEC DDR specifications allows for a 128 GB unbuffered module running at DDR5-6400. RDIMMs and LRDIMMs should be able to go much higher, power permitting.

[...] SK Hynix's announcement today is that they are ready to start shipping DDR5 ECC memory to module manufacturers – specifically 16 gigabit dies built on its 1Ynm process that support DDR5-4800 to DDR5-5600 at 1.1 volts. With the right packaging technology (such as 3D TSV), SK Hynix says that partners can build 256 GB LRDIMMs. Additional binning of the chips for better-than-JEDEC speeds will have to be done by the module manufacturers themselves. SK Hynix also appears to have its own modules, specifically 32GB and 64GB RDIMMs at DDR5-4800, and has previously promised to offer memory up to DDR5-8400.

[...] As part of the announcement, it was interesting to see Intel as one of the lead partners for these modules. Intel has committed to enabling DDR5 on its Sapphire Rapids Xeon processor platform, due for initial launch in late 2021/2022. AMD was not mentioned with the announcement, and neither were any Arm partners.

SK Hynix quotes that DDR5 is expected to be 10% of the global market in 2021, increasing to 43% in 2024. The intersection point for consumer platforms is somewhat blurred at this point, as we're probably only half-way through (or less than half) of the DDR4 cycle. Traditionally we expect a cost interception between old and new technology when they are equal in market share, however the additional costs in voltage regulation that DDR5 requires is likely to drive up module costs – scaling from standard power delivery on JEDEC modules up to a beefier solution on the overclocked modules. It should however make motherboards cheaper in that regard.

See also: Insights into DDR5 Sub-timings and Latencies

Previously: DDR5 Standard to be Finalized by JEDEC in 2018
DDR5-4400 Test Chip Demonstrated
Cadence and Micron Plan Production of 16 Gb DDR5 Chips in 2019
SK Hynix Announces Plans for DDR5-8400 Memory, and More
JEDEC Releases DDR5 Memory Specification


Original Submission

Samsung's 512GB DDR5 Module is a Showcase for the Future of RAM 38 comments

Samsung's 512GB DDR5 module is a showcase for the future of RAM:

Samsung has unveiled a new RAM module that shows the potential of DDR5 memory in terms of speed and capacity. The 512GB DDR5 module is the first to use High-K Metal Gate (HKMG) tech, delivering 7,200 Mbps speeds — over double that of DDR4, Samsung said. Right now, it's aimed at data-hungry supercomputing, AI and machine learning functions, but DDR5 will eventually find its way to regular PCs, boosting gaming and other applications.

[...] With 7,200 Mbps speeds, Samsung's latest module would deliver around 57.6 GB/s transfer speeds on a single channel. In Samsung's press release, Intel noted that the memory would be compatible with its next-gen "Sapphire Rapids" Xeon Scalable processors. That architecture will use an eight-channel DDR5 memory controller, so we could see multi-terabyte memory configurations with memory transfer speeds as high as 460 GB/s. Meanwhile, the first consumer PCs could arrive in 2022 when AMD unveils its Zen 4 platform, which is rumored to support DDR5.

Previously:
SK Hynix Ready to Ship 16 Gb DDR5 Dies, Has Its Own 64 GB DDR5-4800 Modules
JEDEC Releases DDR5 Memory Specification
SK Hynix Announces Plans for DDR5-8400 Memory, and More


Original Submission

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  • (Score: 0) by Anonymous Coward on Friday April 03 2020, @11:34PM (2 children)

    by Anonymous Coward on Friday April 03 2020, @11:34PM (#978898)

    Too bad there's a 7% chance you won't live to see it released.

  • (Score: 2) by DannyB on Saturday April 04 2020, @06:41PM (2 children)

    by DannyB (5839) Subscriber Badge on Saturday April 04 2020, @06:41PM (#979095) Journal

    In Java 15 one of the changes [infoworld.com] will be to increase the maximum heap size from a puny 4 Terabytes of memory up to a decent 16 Terabytes.

    And more cores are always better.

    Faster memory is great too.

    This makes the Java Hello World Enterprise Edition [github.com] run better. It doesn't hurt the Java FizzBuzz Enterprise Edition [github.com] either.

    Now if Java source code could only support animated character glyphs. [soylentnews.org]

    --
    Since nobody defrags SSDs anymore, they are more (or less?) prone to failure of their seek mechanisms.
    • (Score: 2) by takyon on Saturday April 04 2020, @07:53PM (1 child)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday April 04 2020, @07:53PM (#979115) Journal

      Here's a 256 GB RDIMM using 16 Gb dies:

      https://www.anandtech.com/show/13500/samsung-shows-off-256-gb-ddr4-rdimm-coming-to-servers-soon [anandtech.com]

      With 64 Gb dies, that's a quadrooplin' to 1 TB per DIMM.

      There are server motherboards with 16 DIMM slots [hothardware.com].

      So it won't be more than 2-3 years before some Java customers are using that full 16 TB of DDR5 RAM on a single workstation.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 2) by DannyB on Saturday April 04 2020, @08:03PM

        by DannyB (5839) Subscriber Badge on Saturday April 04 2020, @08:03PM (#979121) Journal

        So it won't be more than 2-3 years before some Java customers are using that full 16 TB of DDR5 RAM on a single workstation.

        I can't vouch for the 2-3 years, but people should not laugh. We've come so far, sometimes it's good to look back down. In 1975 an Altair 8800 with an 8080 processor and 256 bytes of memory cost significant money.

        --
        Since nobody defrags SSDs anymore, they are more (or less?) prone to failure of their seek mechanisms.
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