TSMC Has Started The Development of The 2nm Lithography Process
Earlier this month, we saw that TSMC was getting its CoWoS interposer and 5nm production lines at full capacity. Yesterday, we found out that AMD and Nvidia bought up all of their excess capacity for next-generation GPU and CPU development. They have also been making advancements in 3nm process development, but have not been able to put much work in because many of the tools necessary are currently unavailable or hard to find due to the COVID-19 pandemic. 3nm is already a lot of work as it is, but in a recent shareholders meeting, DigiTimes was able to figure out that TSMC is already planning to start the development of the 2nm Lithographic process.
TSMC's "3nm" node has reportedly been delayed by 6 months due to the pandemic. Samsung is facing similar delays on their own "3nm" node.
TSMC's "5nm" production has not been delayed, and AMD will reportedly use an exclusive enhanced "5nm" node for Zen 4 CPUs in 2021.
Previously: TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
High Demand Reported for TSMC's Chip-on-Wafer-on-Substrate Packaging
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TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles
TSMC and Broadcom have also been playing with the idea of oversized chips, and this week they've announced their plans to develop a supersized interposer to be used in Chip-on-Wafer-on-Substrate (CoWoS) packaging.
Overall, the proposed 1,700 mm² interposer is twice the size of TSMC's 858 mm² reticle limit. Of course, TSMC can't actually produce a single interposer this large all in one shot – that's what the reticle limit is all about – so instead the company is essentially stitching together multiple interposers, building them next to each other on a single wafer and then connecting them. The net result is that an oversized interposer can be made to function without violating reticle limits.
The new CoWoS platform will initially be used for a new processor from Broadcom for the HPC market, and will be made using TSMC's EUV-based 5 nm (N5) process technology. This system-in-package product features 'multiple' SoC dies as well as six HBM2 stacks with a total capacity of 96 GB. According to Broadcom's press release, the chip will have a total bandwidth of up to 2.7 TB/s, which is in line with what Samsung's latest HBM2E chips can offer.
Also at Guru3D.
Previously: TSMC Shows Off Gigantic Silicon Interposer
Report: TSMC CoWoS Production Line at Full Capacity as Demand Increases
Despite the downturn of events around the world, TSMC is witnessing a significant increase in demand for its Chip-on-Wafer-on-Substrate (CoWoS) packaging, according to DigiTimes' unnamed industry sources. The Taiwanese silicon manufacturer is purportedly running its CoWoS production lines at full capacity.
CoWoS as is a 2.5D method of packaging multiple individual dies side-by-side on a single silicon interposer. The benefits are the ability to increase the density in small devices as you run into the limits of how big individual dies can be produced, better interconnectivity between dies and lower power consumption.
According to DigiTimes, AMD, Nvidia, HiSilicon, Xilinx and Broadcom have placed orders for the tech, with demand for high-performance computing chips, high bandwidth memory (HBM)-powered AI accelerators and ASICs during the past two weeks.
Examples of CoWoS packaged silicon are [...] AMD's Vega VII graphics cards, as well as Nvidia's V100 cards, which have HBM on the same silicon interposer where the GPU is. With the GPU and memory so close together, memory bandwidth is significantly higher on these chips compared to those using GDDR6 memory located elsewhere on the graphics card's PCB. Additionally, the PCB becomes much smaller.
Also at Wccftech.
Previously: TSMC Shows Off Gigantic Silicon Interposer
TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
TSMC to build a $12 billion advanced semiconductor plant in Arizona with U.S. government support
Taiwan Semiconductor Manufacturing Co., the world's largest contract semiconductor foundry, said today that it plans to build an advanced chip foundry in Arizona with support from the state and the United States federal government.
The announcement follows a Wall Street Journal report earlier this week that White House officials were in talks with TSMC and Intel to build foundries in the U.S., as part of its effort to reduce reliance on chip factories in Asia. Based in Hsinchu, Taiwan, TSMC provides chip components for many of the world's largest semiconductor companies and its U.S. clients include Apple and Qualcomm.
The plant, scheduled to start production of chips in 2024, will enable TSMC's American customers to fabricate their semiconductor products domestically. It will use the company's 5-nanometer technology and is expected to create 1,600 jobs and have the capacity to produce 20,000 wafers a month.
The U.S.-China trade war, national security concerns, geopolitical unrest and the COVID-19 pandemic have all underscored the shortfalls of relying on foundries located abroad and international supply chains.
The U.S. government has reportedly been in talks with TSMC for months, though one sticking point for the company was the high cost of building a new foundry. TSMC chairman Mark Liu told the New York Times in October that the project would require major subsidies because it is more expensive to operate a factory in the U.S. than in Taiwan.
Also at AnandTech, The Verge, CNN, South China Morning Post, Wccftech, and Bloomberg.
Previously: U.S. Attempting to Restrict TSMC Sales to Huawei
Washington in Talks with Chipmakers about Building U.S. Factories
Related: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Has Started Development of a "2nm" Process Node
(Score: 2) by bzipitidoo on Saturday April 25 2020, @06:52PM (6 children)
Meanwhile, what's the oldest node that's still worth using? I have a 65nm Intel and a 45nm AMD from the late 2000s. They are 64bit, but they don't have SSE4. For quite a while, I held off replacing them. Wanted to go with AMD, but AMD wasn't making competitive chips at that time. Finally I refused to wait any longer, and got 14nm Intel. Of course that's when AMD finally got back in the game, with Zen.
Now, hmm... 2nm, huh? What's the thinking on the lower limit now? I vaguely recall hearing that they weren't sure going below 3nm would be possible.
Doesn't sound like they're taking Spectre seriously enough to completely rid their CPUs of it. They just push out "mitigations".
I've never felt great about when I choose to upgrade. No matter when you do it, there's always a whole bunch of new stuff in the works that you won't get.
(Score: 4, Interesting) by takyon on Saturday April 25 2020, @07:42PM (4 children)
The architecture matters more than the node. "32nm" is not so horrible, but you wouldn't want to use an AMD Bulldozer FX-4170 these days.
Barring severe technical problems, new nodes should be better than older ones. What we have seen is that Intel's initial "10nm" node had bad yields or worse thermal performance than an optimized "14nm++++..." node, leading to lower clock speeds. So low power chips were prioritized on the bad node. Intel has gotten "10nm" under control and wants to move quickly to "7nm".
TSMC seems to be making consistent progress, with each node bringing substantial benefits. TSMC "5nm" [anandtech.com] appears to have a ~84% density improvement over TSMC "7nm", which could mean more cores, smaller chips (cheaper to make), more graphics cores on APUs, etc. It can also raise clock speeds, use less power, or a little of both.
AMD's Zen 2 uses "7nm", Zen 3 will use an enhanced "7nm" node this year (roughly September launch), and Zen 4 will skip regular "5nm" and move directly to a custom enhanced TSMC "5nm" node (perhaps 5-10% better than regular "5nm"). They can do this because they have become one of TSMC's largest customers (particularly with next-gen console chips this year), boosted TSMC's stature, and Huawei has fallen out of favor [scmp.com].
I put the node names in quotes because they don't actually mean anything anymore. They are marketing terms and no particular feature size will be 1/2/3/5/7 nanometers in size. But as long as transistor density is increasing, there is still some scaling going on. Intel has put "5nm", "3nm", "2nm", and "1.4nm" [soylentnews.org] on their roadmap. You might expect something in the ballpark of a 100x transistor density increase between "14nm" and "1.4nm", perhaps less.
Old nodes could get new life breathed into them. The answer is monolithic 3D chips [darpa.mil]. A "90nm" 3D chip could vastly outperform a "7nm" 2D chip. That development would reset the clock for Moore's law scaling, or deliver an inconceivable one-time performance improvement.
The choice of when to upgrade (to AMD) this time around depends on the socket change. Zen, Zen+, Zen 2, and Zen 3 chips are compatible with the AM4 socket and use DDR4 memory. Zen 4 will break compatibility, use an AM5 socket, and DDR5 memory. Zen 4 will probably increase core counts (such as 24 cores instead of 16 cores for the top Ryzen), will add PCIe 5.0 support, is rumored to support AVX-512 instructions, may include a large L4 cache, and more. On the other hand, AM4 motherboards, Zen 2/3 chips, and DDR4 memory should become a lot cheaper as Zen 4 comes out. So if you don't want to wait up to a year after Zen 4 launches for prices to drop, maybe you go with the dead-end AM4 socket instead and pick up some clearance deals and (I assume) dirt-cheap DDR4.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by bzipitidoo on Saturday April 25 2020, @08:35PM (3 children)
Yes, architecture matters a great deal. A 1990 CPU such as the 80486, scaled down to a 14nm node, will be vastly inferior to a 2020 CPU at 14nm, even if, for fairness, you limit the 2020 chip to one core. It's still 64bit vs 32bit, and the newer one has a ton of enhancements such as the MMX and SSE instructions, ability to talk to faster buses (PCIe vs ISA with, possibly, VESA Local Bus), a whole lot more cache, and all the pipelining, out-of-order execution, branch prediction, and, uh, yeah, speculative execution. What would the performance difference still be, if the 486 was put on an even footing? Perhaps 10x?
But as you say, marketing has rendered node size meaningless. Maybe a better measure would be average number of transistors per sq mm? I don't doubt that whatever measure anyone manages to invent, they'll find ways to game it.
More issues with the decade old boxes is that they can't use a 128G flash drive, the USB ports are only 2.0, the display interface is DVI (still okay for now), they don't have much RAM by today's standards, and who knows how much longer the aging hard drives will last? Oh yeah, they're also power hungry.
(Score: 2) by takyon on Saturday April 25 2020, @10:31PM (2 children)
Scaling down without doing anything to the design can get you decreased power consumption and maybe clock speed boosts. An example being game consoles like PS3 that got slim versions. The PS3 Cell processor went from 90 to 65 to 45nm, and the GPU went from 90 to 65 to 40 to 28nm.
For an i486, maybe you need to make some design changes to even accommodate multi-GHz clock speeds. And you could shrink the die size from 165 mm2 [cpu-world.com] (1.2 million transistors [jimdofree.com]) to... 0.01 mm2 or less.
Yes, transistors per mm2 is good info. The AnandTech article I linked says 96.27 million transistors per mm2 for TSMC "7nm", and 177.14 mTr/mm2 for TSMC "5nm", which is where the 84% improvement comes from. One benefit I forgot to mention is reduced latency from having denser and closer cores, SRAM, etc. You can also increase the amount of cache without impacting latency as much.
Raspberry Pi 4, although it has limitations, can smoke a lot of those 90s and early 2000s desktop systems. The single-board computers and slightly larger form factors stand to gain big if 3DSoC makes it out of the fab, since it could deliver HEDT performance at single digit wattage. If we accept that computer performance is already good enough for most users, then we will see power consumption cut by 90-99%, and then performance increased on top of that.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Saturday April 25 2020, @11:14PM (1 child)
Parent said:
"Scaling down without doing anything to the design can get you decreased power consumption..."
This was only a certainty for the 20th century. Past a certain size, parasitic (leakage) effects started to dominate. You could no longer "just shrink" the same lithography. Different transistor architectures such as FinFET, silicon on insulator, etc. had to be invented to mitigate the massive power waste that was occurring from shrunk, "old school" transistor designs. Now, with the new and improved transistor designs, do size shrinks tend to reduce power? Yes, but it's not a given it will automatically happen. At these small sizes, managing power leakage is a challenge.
(Score: 3, Informative) by takyon on Saturday April 25 2020, @11:45PM
Ok, so changes happen to transistor designs on the new nodes to make them work. FinFET, GAAFET, etc. TSMC has had a pretty good track record [anandtech.com] (see table) of each node reducing power consumption at the same clock speed. Looks like 87.2% reduction from "20SOC" to "5FF".
For the hypothetical of shrinking the 486, you would have to make changes to get it on "5nm" or "3nm".
AMD and many other chip designers are fabless. They can sign a contract with TSMC, Samsung, GlobalFoundries, or even Intel, and hopefully companies like SkyWater soon (monolithic 3D at larger nodes). If there weren't any improved nodes available, they would just sit on the same node but take advantage of improved yields and better binning, or make bigger changes to the architecture.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 3, Informative) by takyon on Saturday April 25 2020, @11:49PM
Transistor Options Beyond 3nm [semiengineering.com]
5/3nm Wars Begin [semiengineering.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]