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posted by martyb on Wednesday June 17 2020, @04:31PM   Printer-friendly
from the falconry++ dept.

On July 7, AMD will launch three refreshed Zen 2 "Matisse" desktop CPUs with slightly higher boost clocks than the previous versions:

  • 12-core Ryzen 9 3900XT will boost to 4.7 GHz, instead of 4.6 GHz for the 3900X.
  • 8-core Ryzen 7 3800XT will boost to 4.7 GHz, instead of 4.5 GHz for the 3800X.
  • 6-core Ryzen 5 3600XT will boost to 4.5 GHz, instead of 4.4 GHz for the 3600X.

The 3900XT and 3800XT will not come with a bundled cooler, unlike the 3900X and 3800X (the top-of-the-line 16-core 3950X also did not come with a cooler). 3600XT will come with a Wraith Spire cooler.

The "suggested etailer price" (SEP) is the same as the launch prices for the previous CPUs ($499, $399, $249), but the 3900X is often sold for $400-$420 instead of $500, for example. So customers may end up paying between 10-25% more for a 2-5% potential performance gain, unless retailers drop the prices soon after launch.

The new 3000XT family of processors focuses mostly on boosting the turbo frequency by 100-200 MHz for the same power. AMD states that this is due to using an optimized 7nm manufacturing process. This is likely due to a minor BKM[*] or PDK[**] update that allows TSMC/AMD to tune the process for a better voltage/frequency curve and bin a single CPU slightly higher.

[...] In each [of the] three cases, the XT processors give slightly better frequency than the X units, so we should expect to see an official permanent price drop on the X processors in order to keep everything in line.

The CPUs should work with existing motherboards that supported the non-XT CPUs, after a BIOS update.

A September to October 2020 launch date is likely for the first next-generation Ryzen 4000 Zen 3 "Vermeer" CPUs. Rumors of the launch being pushed back to 2021 have been denied.

[*] BKM: Best-Known Method
[**] PDK: Process Design Kit


Original Submission

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AMD Announces Zen 3 CPUs 28 comments

AMD announced its first Zen 3 (Ryzen 5000 series) desktop CPUs on October 8.

Compared to Zen 2 (Ryzen 3000 series) CPUs, the Zen 3 microarchitecture has higher boost clocks and around 19% higher instructions per clock. A unified core complex die (CCD) allows 8 cores to access up to 32 MB of L3 cache, instead of two groups of 4 cores accessing 16 MB each, leading to lower latency and more cache available for any particular core. TDPs are the same as the previous generation, leading to a 24% increase in performance per Watt.

AMD estimates a 26% average increase in gaming performance at 1080p resolution, with the Zen 3 CPUs beating or tying Intel's best CPUs in most games.

Ryzen 9 5950X, 16 cores, 32 threads, boosts up to 4.9 GHz, 105W TDP, $800.
Ryzen 9 5900X, 12 cores, 24 threads, boosts up to 4.8 GHz, 105W TDP, $550.
Ryzen 7 5800X, 8 cores, 16 threads, boosts up to 4.7 GHz, 105W TDP, $450.
Ryzen 5 5600X, 6 cores, 12 threads, boosts up to 4.6 GHz, 65W TDP, $300.

You may have noticed that these prices are exactly $50 more than the launch prices for the Ryzen 3000 equivalents released in 2019. The 5600X is the only model that will ship with a bundled cooler.

The CPUs will all be available starting on November 5. AMD will stream an announcement for its RX 6000 series of high-end GPUs on October 28.

See also: AMD Zen 3 Announcement by Lisa Su: A Live Blog at Noon ET (16:00 UTC)
AMD Teases Radeon RX 6000 Card Performance Numbers: Aiming For 3080?

Previously: AMD's Zen 3 CPUs Will Not be Compatible with X470, B450, and Older Motherboards
AMD Reverses BIOS Decision, Intends to Support Zen 3 on B450 and X470 Motherboards
AMD Launching 3900XT, 3800XT, and 3600XT Zen 2 Refresh CPUs: Milking Matisse
AMD Zen 3, Ryzen 4000 Release Date, Specifications, Performance, All We Know


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  • (Score: 2) by Booga1 on Wednesday June 17 2020, @10:15PM (3 children)

    by Booga1 (6333) on Wednesday June 17 2020, @10:15PM (#1009314)

    Some people can't wait! Other's can't wait. Just helped a friend sort out making purchases for a new build over the last month. He's the type that would totally pay the extra money for that 5% performance, but all the purchases were finalized last week. I warned him this was right around the corner, but he just had to have his stuff right now.

    It is nice to hear that the Zen 3 launch has not been pushed back completely. I do wonder if it will have a staggered release or other effects due to the coronavirus. It was hard enough getting a motherboard since some retailers were 100% out of stock on various motherboards for at least a month. One place ran out of every single AMD X570 board.

    • (Score: 2) by takyon on Thursday June 18 2020, @01:55AM (2 children)

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Thursday June 18 2020, @01:55AM (#1009387) Journal

      Zen 2 was a staggered release. The main chips came out in July 2019, but 3950X was pushed to late November. And then the 3100/3300X quad-cores came out this April.

      Coronavirus effects may add up to only a month at worse. A lot of the pieces for Zen 3 were in place far in advance. It's stuff like TSMC's "3nm" node [wccftech.com] that might take the hit.

      These refresh chips don't make too much sense yet. Maybe they will result in better than expected benchmarks, by hitting the top clock speeds for longer or something. But for now, expect just 2-5% gain. Zen 3 actually has a chance of seizing the gaming crown, and no delay to January means another 2-3 months of pain for Intel.

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      • (Score: 0) by Anonymous Coward on Thursday June 18 2020, @05:43PM (1 child)

        by Anonymous Coward on Thursday June 18 2020, @05:43PM (#1009613)

        These refresh chips don't make too much sense yet.

        I think that's unfair. AMD's yields were high enough, and the manufacturing process sufficiently squared-away that it made sense to sell the chips a little faster than was prac tical at the initial launch. That sort of speed boost when manufacturing gets tweaked is pretty normal. Obviously, nobody is going to upgrade from the immediately previous model just for this extra few percent. But if you were shopping for a computer with a $350 CPU today vs. a month ago, the one you buy today will now be a little bit faster for the same price. Or the computer you would have bought a month ago will now be a few dollars cheaper. Yay. progress.

  • (Score: 0) by Anonymous Coward on Thursday June 18 2020, @01:33AM (1 child)

    by Anonymous Coward on Thursday June 18 2020, @01:33AM (#1009378)

    My phenom 8-core rig is still running fine.

    You ain't gonna make me ...

  • (Score: 0) by Anonymous Coward on Thursday June 18 2020, @05:22PM (3 children)

    by Anonymous Coward on Thursday June 18 2020, @05:22PM (#1009597)

    so does it have quad-channel already?

    • (Score: 1, Informative) by Anonymous Coward on Thursday June 18 2020, @05:37PM (1 child)

      by Anonymous Coward on Thursday June 18 2020, @05:37PM (#1009605)

      The higher-end Threadripper parts have Quad channel memory. I don't think you'll see it on the cheaper mainstream CPU's any time soon, because it's not an artificial market segmentation trick. Extra memory channels means the socket needs to physically have pins for all those extra channels, and the motherboard needs traces for the separate bus, etc.. Motherboards with the big quad-channel socket are always going to be more expensive than duial-channel counterparts. And the biggest need for the extra bandwidth is always going to come from systems with the most cores trying to fetch data to work with. Until somebody comes up with a serial memory interface that somehow clocks insanely fast (And there are some real laws of physics that you come up against trying to engineer something reliable at that high frequency range with normal materials.), the mainstream parts are going to have less memory channels than the high end.

      Certainly, as long as AMD is using the current socket for mainstream chips, you won't see it magically grow support for 4 channels, even if the CPU die has unconnected pads that would theoretically support it. It's physically impossible for this kind of backward-compatible clock bump to add support for it.

      • (Score: 3, Informative) by takyon on Thursday June 18 2020, @06:45PM

        by takyon (881) <{takyon} {at} {soylentnews.org}> on Thursday June 18 2020, @06:45PM (#1009652) Journal

        Get ready for DDR5 channel inflation:

        https://www.micron.com/-/media/client/global/documents/products/white-paper/ddr5_more_than_a_generational_update_wp.pdf [micron.com]

        In addition to higher data rates and improvements to the I/O circuitry, DDR5 introduces other new protocol features unrelated to data rate that are integral to increasing bandwidth and performance. For example, DDR5 DIMMs feature two 40-bit (32 bits plus ECC) independent channels. When combined with a new default burst length of 16 (BL16) in the DDR5 component, this allows a single burst to access 64B of data (the typical CPU cache line size) using only one of the independent channels, or only half of the DIMM. Providing this ability to interleave accesses from these two independent channels enables tremendous improvements to concurrency, essentially turning an 8-channel system as we know it today into a 16-channel system.

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    • (Score: 2) by takyon on Thursday June 18 2020, @06:24PM

      by takyon (881) <{takyon} {at} {soylentnews.org}> on Thursday June 18 2020, @06:24PM (#1009638) Journal

      There were rumors that Threadripper 3000 would get 8-channel variants, but that never materialized.

      If there is going to be any change for the mainstream Ryzen CPUs, that would come on the new AM5 socket (starting with Zen 4, probably in early 2022), which will use DDR5 memory.

      It's worth noting:

      DDR5 [wikipedia.org] supports a speed of 51.2 GB/s per module and 2 memory channels per module.

      What does that mean? Take it from Rambus: [rambus.com]

      Another major change with DDR5, number four on our list, is a new DIMM channel architecture. DDR4 DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels. Each of these channels will be 40-bits wide: 32 data bits with eight ECC bits. While the data width is the same (64-bits total) having two smaller independent channels improves memory access efficiency. So not only do you get the benefit of the speed bump with DDR5, the benefit of that higher MT/s is amplified by greater efficiency.

      In the DDR5 DIMM architecture, the left and right side of the DIMM, each served by an independent 40-bit wide channel, share the RCD. In DDR4, the RCD provides two output clocks per side. In DDR5, the RCD provides four output clocks per side. The 32-bit data of each 40-bit channel consist of four 8-bit lanes, and each of these lanes gets an independent clock signal from the RCD. Giving each lane an independent clock improves signal integrity, helping to address the lower noise margin issue raised by lowering the VDD (from change #2 above).

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