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posted by martyb on Friday August 07 2020, @06:29AM   Printer-friendly
from the intel-on-Intel dept.

What's wrong with Intel, and how to fix it: Former principal engineer unloads (archive)

In a blunt video posted late Thursday evening, outspoken former Intel principal engineer Francois Pidnoel offered his advice on how to "fix" Intel CPUs, criticized current leadership for not being engineers, said AVX512 was a misadventure, and declared that it's only luck AMD hasn't grabbed more market share.

"First, Intel is really out of focus," Piednoel said in the nearly hour-long video presentation. "The leaders of Intel today are not engineers, they are not people who understand what to design to the market."

[...] Pidnoel flat-out dismissed including AVX512 in consumer chips as a mistake. "You had Skylake and Skylake X for a reason," Piednoel said. "AVX512 is designed for a race of throughput that is lost to the GPU already. There's two ways to get throughput. One is to get the throughput is by having larger vectors to your core, and the other way is to have more cores."

[...] "Intel is very lucky AMD cannot get the volume, to be able to compete," Piednoel. "If they were getting volume, the price difference would definitely cost Intel market share a lot more than what they are losing right now."

Related: AVX-512: A "Hidden Gem"?
Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021
Intel's Process Nodes Will Trail Behind Competitors Until at Least Late 2021
Linus Torvalds: Don't Hide Rust in Linux Kernel; Death to AVX-512
Intel Engineering Chief Out After 7nm Product Delays
Intel Faces Class-Action Lawsuit Over "7nm" Delays

Original Submission

Related Stories

AVX-512: A "Hidden Gem"? 6 comments

Upcoming Intel processors will support scalable AVX-512 instructions, which one former Intel employee calls a "hidden gem":

Imagine if we could use vector processing on something other than just floating point problems. Today, GPUs and CPUs work tirelessly to accelerate algorithms based on floating point (FP) numbers. Algorithms can definitely benefit from basing their mathematics on bits and integers (bytes, words) if we could just accelerate them too. FPGAs can do this, but the hardware and software costs remain very high. GPUs aren't designed to operate on non-FP data. Intel AVX introduced some support, and now Intel AVX-512 is bringing a great deal of flexibility to processors. I will share why I'm convinced that the "AVX512VL" capability in particular is a hidden gem that will let AVX-512 be much more useful for compilers and developers alike.

Fortunately for software developers, Intel has done a poor job keeping the "secret" that AVX-512 is coming to Intel's recently announced Xeon Scalable processor line very soon. Amazon Web Services has publically touted AVX-512 on Skylake as coming soon!

It is timely to examine the new AVX-512 capabilities and their ability to impact beyond the more regular HPC needs for floating point only workloads. The hidden gem in all this, which enables shifting to AVX-512 more easily, is the "VL" (vector length) extensions which allow AVX-512 instructions to behave like SSE or AVX/AVX2 instructions when that suits us. This is a clever and powerful addition to enable its adoption in a wider assortment of software more quickly. The VL extensions mean that programmers (and compilers) do not need to shift immediately from 256-bits (AVX/AVX2) to 512-bits to use the new bit/byte/word manipulations. This transitional benefit is useful not only for an interim, but also for applications which find 256-bits more natural (perhaps a small, but important, subset of problems).

Will it be enough to stave off "Epyc"?

Original Submission

Intel CEO Blames "10nm" Delays on Aggressive Density Target, Promises "7nm" for 2021 10 comments

Intel says it was too aggressive pursuing 10nm, will have 7nm chips in 2021

[Intel's CEO Bob] Swan made a public appearance at Fortune's Brainstorm Tech conference in Aspen, Colorado, on Tuesday and explained to the audience in attendance that Intel essentially set the bar too high for itself in pursuing 10nm. More specifically, he pointed to Intel's overly "aggressive goal" of going after a 2.7x transistor density improvement over 14nm.

[...] Needless to say, the 10nm delays have caused Intel to fall well behind that transistor density doubling. Many have proclaimed Moore's Law as dead, but as far as Swan is concerned, Moore's Law is not dead. It apparently just needed to undergo an unexpected surgery.

"The challenges of being late on this latest [10nm] node of Moore's Law was somewhat a function of what we've been able to do in the past, which in essence was define the odds on scaling the infrastructure," Swan explains. Bumping up to a 2.7x scaling factor proved to be "very complicated," more so than Intel anticipated. He also says that Intel erred when it "prioritized performance at a time when predictability was really important."

"The short story is we learned from it, we'll get our 10nm node out this year. Our 7nm node will be out in two years and it will be a 2.0X scaling so back to the historical Moore's Law curve," Swan added.

Also at Fortune and Tom's Hardware.


Original Submission

Intel's Process Nodes Will Trail Behind Competitors Until at Least Late 2021 16 comments

Intel Says Process Tech to Lag Competitors Until Late 2021, Will Regain Lead with 5nm (archive)

It appears that 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday covering a wide range of topics, but noted that despite being "undoubtedly in the 10nm era," the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021. Davis also said that Intel wouldn't regain process leadership until it produces the 5nm node at an unspecified date.

Davis commented that the company was "definitely in the 10nm era" with Ice Lake client chips and networking ASICs already shipping, along with the pending release of discrete GPUs and Ice Lake Xeons. Intel is also moving well along the path of inter-node development, which consists of "+" revisions to existing processes. Davis said the 10nm inter-node step provides a "step-function move" with the Tiger Lake chips based on the 10nm+ process as the company awaits its 7nm process.

However, Davis noted that in spite of the shipping products and pending "+" revisions to the 10nm process, its process node still lags behind competitors, stating:

"So we bring a lot of capability to the table for our customers, in addition to the CPU, and we feel like we're starting to see the acceleration on the process side that we have been talking about to get back to parity in the 7nm generation and regain leadership in the 5nm generation."

Intel Launches Coffee Lake Refresh, Roadmap Leaks Showing No "10nm" Desktop Parts Until 2022
Intel's Jim Keller Promises That "Moore's Law" is Not Dead, Outlines 50x Improvement Plan
Intel Roadmap Shows Plans for "5nm", "3nm", "2nm", and "1.4nm" Process Nodes by 2029

Original Submission

Linus Torvalds: Don't Hide Rust in Linux Kernel; Death to AVX-512 50 comments

Linus Torvalds' Initial Comment On Rust Code Prospects Within The Linux Kernel

Kernel developers appear to be eager to debate the merits of potentially allowing Rust code within the Linux kernel. Linus Torvalds himself has made some initial remarks on the topic ahead of the Linux Plumbers 2020 conference where the matter will be discussed at length.

[...] Linus Torvalds chimed in though with his own opinion on the matter. Linus commented that he would like it to be effectively enabled by default to ensure there is widespread testing and not any isolated usage where developers then may do "crazy" things. He isn't calling for Rust to be a requirement for the kernel but rather if the Rust compiler is detected on the system, Kconfig would enable the Rust support and go ahead in building any hypothetical Rust kernel code in order to see it's properly built at least.

Linus Torvalds Wishes Intel's AVX-512 A Painful Death

According to a mailing list post spotted by Phoronix, Linux creator Linus Torvalds has shared his strong views on the AVX-512 instruction set. The discussion arose as a result of recent news that Intel's upcoming Alder Lake processors reportedly lack support for AVX-512.

Torvalds' advice to Intel is to focus on things that matter instead of wasting resources on new instruction sets, like AVX-512, that he feels aren't beneficial outside the HPC market.

Related: Rust 1.0 Finally Released!
Results of Rust Survey 2016
AVX-512: A "Hidden Gem"?
Linus Torvalds Rejects "Beyond Stupid" Intel Security Patch From Amazon Web Services

Original Submission

Intel Engineering Chief Out After 7nm Product Delays 31 comments


Intel is revamping its technology leadership in a bid to turnaround its manufacturing unit after announcing delays in its 7nm processes.

Last week, Intel said on its second quarter earnings report that its 7nm products would be delayed. Rival AMD is already on 7nm as is TSMC. Since Intel's earnings report and market cap hit, analysts have been speculating that the chip giant may leave manufacturing.

In other words, Intel needed to revamp its technology organization. Under Monday's reorg, Dr. Ann Kelleher will lead technology development. She had led Intel manufacturing. Kelleher will focus on developing 7nm and 5nm processes. Murthy Renduchintala, Intel's chief engineering officer, will depart Aug. 3.

Intel is also separating its Technology, Systems Architecture and Client Group unit into teams focused on technology development, manufacturing and operations, design engineering, architecture, software and graphics and supply chain.

Safe to say Intel will be best positioned to fire 3 executives at the next slippage - I guess that may make the stock rebound faster than firing a single one.

Original Submission

Intel Faces Class-Action Lawsuit Over "7nm" Delays 36 comments

Intel facing class-action lawsuit over 7nm delay

Intel's revenue was up 20 percent in its Q2 2020 earnings report, but its 7nm processors have been delayed by at least six months because production has fallen a year behind. The subsequent decline in share price resulted in AMD's stock jumping above its rival's for the first time in around 15 years.

On Friday, the Hagens Berman law firm put out a call to Intel investors who suffered significant losses to contact the company for a possible class-action suit. It also seeks people who may be able to assist in its investigation of possible securities fraud.

"Beginning at the Company's 2019 annual investor conference, Intel continuously represented that it would start shipping its first 7nm chips in 2021. The news was well-received since the Company claimed the 7nm chip would deliver double the area efficiency of its 10nm chips. Moreover, in the wake of severe delays derailing its 10nm chips, Intel assuaged concerns by stating, "We've made time-to-market the priority," and repeatedly affirmed the 7nm chip's timetable," states Hagens Berman.

Also at Guru3D.

Previously: Intel Delays "7nm" Products by 6 Months
Intel Engineering Chief Out After 7nm Product Delays

Original Submission

AnandTech Reviews Intel's i7-11700K "Rocket Lake" CPU Early 14 comments

Intel's next-generation "Rocket Lake" CPUs will be some of Intel's last desktop models on a "14nm" node, and include "backported" Willow Cove cores (referred to as "Cypress Cove") from "10nm" Tiger Lake mobile CPUs, with improved instructions per clock. Notably, the lineup only goes up to 8 cores, instead of 10 cores for the previous Core i9. The review embargo ends on the launch date, March 30th, but some retailers have been selling the CPUs early. AnandTech obtained an 8-core i7-11700K and wrote a review of it. The results were not great.

Power consumption of the 125 W TDP chip peaked at 224.56 W when running an AVX2 workload, compared to 204.79 W for its i7-10700K "Comet Lake" predecessor and 141.45 W for AMD's Ryzen 7 5800X. The i7-11700K reached 291.68 W with an AVX-512 workload.

The i7-11700K not only failed to beat the 5800X in many benchmarks, but trailed the previous-gen i7-10700K in some cases. The major exception is performance in AVX-512 workloads. Gaming performance of the i7-11700K was particularly bad, in part due to an increase in L3 cache and core-to-core latency.

It's possible that there will be some improvements from a final microcode update before launch. There's also models like the Core i9-11900K, which have the same 8 cores but can clock up to 300 MHz higher.

See also: Intel Core i7-11700K 8 Core Rocket Lake CPU Review Published By Anandtech – Very Hot, Consumes More Power Than Core i9-10900K & Slower Than AMD In Core-To-Core Tests

Related: Linus Torvalds: Don't Hide Rust in Linux Kernel; Death to AVX-512
Former Intel Principal Engineer Blasts the Company
Gigabyte Confirms Intel Rocket Lake Desktop CPUs Will Launch in March

Original Submission

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  • (Score: 5, Insightful) by RamiK on Friday August 07 2020, @06:59AM (4 children)

    by RamiK (1813) on Friday August 07 2020, @06:59AM (#1032788)

    It's nice it's finally coming out from an (ex)Intel engineer after people been saying as much for so many years but it's REALLY too late.

    • (Score: 3, Insightful) by takyon on Friday August 07 2020, @07:41AM (2 children)

      by takyon (881) <{takyon} {at} {}> on Friday August 07 2020, @07:41AM (#1032793) Journal
      [SIG] 10/28/2017: Soylent Upgrade v14 []
      • (Score: 3, Interesting) by RamiK on Friday August 07 2020, @09:35AM

        by RamiK (1813) on Friday August 07 2020, @09:35AM (#1032805)

        Looking at the scope, the leak seems to be the ODMs' "support package" for putting together motherboards' firmwares and such so it's not something that they didn't expect AMD and friends getting their hands on it so there shouldn't be any problems there beyond the odd security vulnerability that will get patched eventually. Similarly, the new vulnerability is really just another issue in a long line of issues that will get addressed by microcode and/or software so they'll just brush it off like usual.

        Besides, my too-late isn't just about that: While MBAs making mistakes is part of the problem, Intel keeping AVX512 for so long while going into GPUs is likely due to them realizing they can't balance hyper-threading, SMT and single-threaded the way he suggests since speculative execution redesigns ate away at the relevant optimizations. So, the only way for them to address the market demand for those loads (without giving it all up to nVidia) is to make their own discrete GPU dies and glue a few of them into the Xeons a few years down the line instead of the vector instructions once nVidia's current gamble on ray tracing and AI ends up trivialized like Ageia's PhysX. Also, as I've said on other posts, single-threaded performance just doesn't matter that much for consumers since the GPU is the bottleneck anyhow.

        So, those points he's making now and that we've been raising for years aren't wrong and will improve things if addressed immediately in the short term but they no longer fully address Intel's long term concerns in the consumer market where single threaded performance is either irrelevant or bottlenecked by the GPU, the HPC market where GPUs handle the loads better than the AVX512, or the VM market where the AVX512 costs them 10% die space. They only partially address the latter and that's assuming AMD can't match them with the new Zen on single-threaded.

        Overall, too late.

      • (Score: 2) by shortscreen on Friday August 07 2020, @01:13PM

        by shortscreen (2252) on Friday August 07 2020, @01:13PM (#1032855) Journal

        So the "vulnerability" is that Intel CPUs let you change the voltage again? Two things about this are very strange...

        1) On a Pentium M privileged code could set the voltage to anything covering a very wide range. But on Core2 they locked it down and options became quite limited. Did they open it up again on later CPUs?

        2) Was this documented functionality that was there all along and someone just noticed it could be harmful? (Yeah, right) Or did a 'secret' method of changing the voltage come to light that wasn't supposed to be there?

        TFA is too busy being sensational and explaining voltage for laymen.

    • (Score: 2) by DannyB on Friday August 07 2020, @02:54PM

      by DannyB (5839) Subscriber Badge on Friday August 07 2020, @02:54PM (#1032920) Journal

      but it's REALLY too late.

      I dearly hope so.

      Trump is a poor man's idea of a rich man, a weak man's idea of a strong man, and a stupid man's idea of a smart man.
  • (Score: 1, Interesting) by Anonymous Coward on Friday August 07 2020, @02:02PM (1 child)

    by Anonymous Coward on Friday August 07 2020, @02:02PM (#1032872)

    Did he say that Intel fixed the processor bugs that let the bad guys peek into kernel memory thru speculative execution but that the PR folks didn't understand it was worth telling anybody about it?

    "Fix" in my book would mean without a major performance penalty. That would taken more logic in the processor. They did microcode hacks with penalties initially. Did they actually 'fix' it later?

    • (Score: 2) by Freeman on Friday August 07 2020, @05:57PM

      by Freeman (732) on Friday August 07 2020, @05:57PM (#1033040) Journal

      Beats me. I've been using AMD for a long time and don't plan on stopping. The fact that they weren't as vulnerable to some of those exploits as Intel is just gravy.

      Joshua 1:9 "Be strong and of a good courage; be not afraid, neither be thou dismayed: for the Lord thy God is with thee"
  • (Score: 2) by NateMich on Friday August 07 2020, @03:08PM

    by NateMich (6662) on Friday August 07 2020, @03:08PM (#1032930)

    Man, this guy has been such a jerk, and wrong about Intel for so long, it's really hard for me to listen to anything he says and take him seriously.

  • (Score: 0) by Anonymous Coward on Friday August 07 2020, @09:46PM (1 child)

    by Anonymous Coward on Friday August 07 2020, @09:46PM (#1033180)

    AMD hired a female Asian engineer CEO because she's kick-ass competent. Intel's diversity hires are driven by HR checklists... "we need a pink-haired transvestite in engineering to meet this month's quota... go hire one".

    • (Score: -1, Troll) by Anonymous Coward on Saturday August 08 2020, @03:18AM

      by Anonymous Coward on Saturday August 08 2020, @03:18AM (#1033300)

      "we need a pink-haired transvestite in engineering to meet this month's quota... go hire one".

      You forgot the requirements about being a morbidly obese wheelchair bound paraplegic with diabetes, you bigot.

      Please report to social justice reeducation camp.