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posted by martyb on Wednesday August 19 2020, @08:58PM   Printer-friendly
from the remember-when-2-cores-was-a-big-deal? dept.

Hot Chips 2020: Marvell Details ThunderX3 CPUs - Up to 60 Cores Per Die, 96 Dual-Die in 2021

Today as part of HotChips 2020 we saw Marvell finally reveal some details on the microarchitecture of their new ThunderX3 server CPUs and core microarchitectures. The company had announced the existence of the new server and infrastructure processor back in March, and is now able to share more concrete specifications about how the in-house CPU design team promises to distinguish itself from the quickly growing competition that is the Arm server market.

[...] Marvell started off the HotChips presentation with a roadmap of its products, detailing that the ThunderX3 generation isn't merely just a single design, but actually represents a flexible approach using multiple dies, with the first generation 60-core CN110xx SKUs using a single die as a monolithic design in 2020, and next year seeing the release of a 96-core dual-die variant aiming for higher performance.

The use of a dual-die approach like this is very interesting as it represents a mid-point between a completely monolithic design, and a chiplet approach from vendors such as AMD. Each die here is identical in the sense that it can be used independently as standalone products.

Some details about the CPUs and the 4-way SMT were given in the presentation. TDPs will range from 100 Watts to 240 Watts.

Previously: Marvell Announces ThunderX3, an ARM Server CPU With 96 Cores, 384 Threads


Original Submission

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The Arm server ecosystem is well alive and thriving, finally getting into serious motion after several years of false-start attempts. Among the original pioneers in this space was Cavium, which went on to be acquired by Marvell in 2018. Among the company's server CPU products is the ThunderX line; while the first generation ThunderX left quite a lot to be desired, the ThunderX2 was the first Arm server silicon that we deemed viable and competitive against Intel and AMD products. Since then, the ecosystem has accelerated quite a lot, and only last week we saw how impressive the new Amazon Graviton2 with the N1 chips ended up. Marvell didn't stop at the ThunderX2, and had big ambitions for its newly acquired CPU division, and today is announcing the new ThunderX3.

The ThunderX3 is a continuation and successor to then-Cavium's custom microarchitecture found in the TX2, adopting a lot of the key characteristics, most notably the capability of 4-way SMT. Adopting a new microarchitecture with higher IPC capabilities, the new TX3 also ups the clock frequencies, and now hosts up to a whopping 96 CPU cores, allowing the chip to scale up to 384 threads in a single socket.

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Original Submission

Marvell Announces PCIe 5.0 SSD Controllers Capable of 14 GB/s Sequential Reads 10 comments

Marvell Announces First PCIe 5.0 NVMe SSD Controllers: Up To 14 GB/s

Today Marvell is announcing the first NVMe SSD controllers to support PCIe 5.0, and a new branding strategy for Marvell's storage controllers. The new SSD controllers are the first under the umbrella of Marvell's Bravera brand, which will also encompass HDD controllers and other storage accelerator products. The Bravera SC5 family of PCIe 5.0 SSD controllers will consist of two controller models: the 8-channel MV-SS1331 and the 16-channel MV-SS1333.

These new SSD controllers roughly double the performance available from PCIe 4.0 SSDs, meaning sequential read throughput hits 14 GB/s and random read performance of around 2M IOPS. To reach this level of performance while staying within the power and thermal limits of common enterprise SSD form factors, Marvell has had to improve power efficiency by 40% over their previous generation SSD controllers. That goes beyond the improvement that can be gained simply from smaller fab process nodes, so Marvell has had to significantly alter the architecture of their controllers. The Bravera SC5 controllers still include a mix of Arm cores (Cortex-R8, Cortex-M7 and a Cortex-M3), but now includes much more fixed-function hardware to handle the basic tasks of the controller with high throughput and consistently low latency.

Top-of-the-line PCIe 4.0 controllers from Phison and Silicon Motion are capable of 7.4 GB/s of sequential reads.

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  • (Score: 2) by requerdanos on Wednesday August 19 2020, @09:23PM (3 children)

    by requerdanos (5997) Subscriber Badge on Wednesday August 19 2020, @09:23PM (#1039049) Journal

    I wonder if Alibaba XT910 RISC-V still wants to be compared with ARM when this CPU is entered into the conversation.

    For that matter, I wonder whether there are meaningful benchmarks able to compare the two, were samples to be had.

  • (Score: 0) by Anonymous Coward on Wednesday August 19 2020, @09:44PM (2 children)

    by Anonymous Coward on Wednesday August 19 2020, @09:44PM (#1039057)

    Semiconductor industry seems to be on "full speed ahead" - what pandemic?

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