from the smaller-and-smaller dept.
Taiwan Semiconductor Manufacturing Company (TSMC) announced a number of node scaling details and technological advancements at its 2020 Technology Symposium:
TSMC's first "5nm" node (N5) has a lower defect rate than its initial "7nm" node did at the same point in its development cycle (high volume manufacturing, which N5 is now in). This is due in part to increasing use of extreme ultraviolet lithography (EUV). "5nm" will represent 11% of TSMC's sub-"16nm" wafer production in 2020.
TSMC's "3nm" node (N3) will continue to use FinFETs rather than gate-all-around (GAA) transistors, and is scheduled for volume production in mid-late 2022. Performance is expected to improve 10-15% at the same power (compared to N5), or power consumption will be reduced 25-30% for the same performance. Logic area density improvement will be 1.7x, but SRAM density will only increase by 1.2x, leading to a 1.27x overall density increase for chips that are 70% SRAM and 30% logic.
Intel's EMIB (Embedded Die Interconnect Bridge) connects "chiplets" together without using a full silicon interposer. TSMC has its own version that it is calling Local Si Interconnect (LSI), and it will be combined with other packaging technologies. TSMC has demonstrated 12-layer stacking of chips using through silicon vias (TSVs), although cooling or doing anything useful with them could be somebody else's job.
See also: TSMC Updates on Node Availability Beyond Logic: Analog, HV, Sensors, RF
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Intel will be using a few packaging technologies to connect CPU core "chiplets":
Intel revealed three new packaging technologies at SEMICON West: Co-EMIB, Omni-Directional Interconnect (ODI) and Multi-Die I/O (MDIO). These new technologies enable massive designs by stitching together multiple dies into one processor. Building upon Intel's 2.5D EMIB and 3D Foveros tech, the technologies aim to bring near-monolithic power and performance to heterogeneous packages. For the data-center, that could enable a platform scope that far exceeds the die-size limits of single dies.
[...] Compared to interposers, which can be reticle-sized (832mm2) or even larger, [EMIB (Embedded Multi-die Interconnect Bridge)] is just a small (hence, cheap) piece of silicon. It provides the same bandwidth and energy-per-bit advantages of an interposer compared to standard package traces, which are traditionally used for multi-chip packages (MCPs), such as AMD's Infinity Fabric. (To some extent, because the PCH is a separate die, chiplets have actually been around for a very long time.)
[...] Intel showed off a concept product that contains four Foveros stacks, with each stack having eight small compute chiplets that are connected via TSVs to the base die. (So the role of Foveros there is to connect the chiplets as if it were a monolithic die.) Each Foveros stack is then interconnected via two (Co-)EMIB links with its two adjacent Foveros stacks. Co-EMIB is further used to connect the HBM and transceivers to the compute stacks.
Evidently, the cost of such a product would be enormous, as it essentially contains multiple traditional monolithic-class products in a single package. That's likely why Intel categorized it as a data-centric concept product, aimed mainly at the cloud players that are more than happy to absorb those costs in exchange for the extra performance.
[...] When they are ready, these technologies will provide Intel with powerful capabilities for the heterogeneous and data-centric era. On the client side, the benefits of advanced packaging include smaller package size and lower power consumption (for Lakefield, Intel claims a 10x SoC standby power improvement at 2.6mW). In the data center, advanced packaging will help to build very large and powerful platforms on a single package, with performance, latency, and power characteristics close to what a monolithic die would yield. The yield advantage of small chiplets and the establishment of chipset ecosystem are major drivers, too.
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AMD announced the Radeon RX 6800M, 6700M, and 6600M discrete GPUs for laptops, promising better performance, efficiency, and battery-constrained performance. The Radeon RX 6800M is a 40 compute unit design (equivalent to the Radeon RX 6700 XT on desktop) with 12 GB of VRAM.
AMD biggest announcements were the introduction of FidelityFX Super Resolution (FSR) and the demonstration of a 3D chiplet design. FSR uses a spatial scaling algorithm to upscale game graphics for higher frame rates at a given resolution. The algorithm competes with Nvidia's Deep Learning Super Sampling (DLSS), but will be released as open source and work with some older AMD GPUs, integrated graphics, as well as competing products from Nvidia and Intel (it was shown running on an Nvidia GTX 1060).
AMD CEO Lisa Su also showed off a modified, delidded Ryzen 9 5900X CPU prototype, with "3D V-Cache technology". It was identical to the standard 5900X with the exception of through-silicon via (TSV) stacked L3 cache. This allowed the 5900X prototype to have 192 MB of total L3 cache instead of 64 MB (96 MB per 8-core chiplet). AMD claims it can run games with an average of +15% performance (simply due to the larger cache size), and some version of this will appear in products that are starting production at the end of 2021.