SiFive to Debut a RISC-V PC for Developers in October

SiFive Introduces RISC-V Linux-Capable Multicore Processor 29 comments

Submitted via IRC for TheMightyBuzzard

Slowly but surely, RISC-V, the Open Source architecture for everything from microcontrollers to server CPUs is making inroads in the community. Now SiFive, the major company behind putting RISC-V c...

That's damned nifty but at a grand for a 1.5GHz system, I don't see them selling that many to consumers.

Source: https://hackaday.com/2018/02/03/sifive-introduces-risc-v-linux-capable-multicore-processor/

Original Submission

SiFive HiFive Unleashed Not as Open as Previously Thought 17 comments

lordtaw writes:

Spotted over on Phoronix:

While free software/hardware advocates have been ecstatic about the RISC-V open-source, royalty-free processor architecture, hardware so far hasn't been as open as desired.
While this processor ISA is entirely open and living up to its merits, it turns out the RISC-V implementations so far haven't been quite as open as one would have thought. A Phoronix reader pointed out to us some remarks by developers on the main RISC-V development board out so far, the SiFive HiFive Unleashed
Ron Minnich who has run the Coreboot project for more than the past decade and spearheads the effort of getting Coreboot on new Chrome OS devices at Google, commented on the Unleashed development board this weekend:
All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive.
Open instruction sets do not necessarily result in open implementations. An open implementation of RISC-V will require a commitment on the part of a company to opening it up at all levels, not just the instruction set.

The issue stems from the use of third party IP used to complete the SoC as Risc-V is an instruction set, not a physical hardware design. The actual silicon of the CPU must be designed in order to implement the instruction set as actual hardware and glue logic to tie the CPU to other hardware like memory and bus controllers. In the case, the HiFive Unleashed features a DRAM controller from Cadence which uses a proprietary binary blob to initialize the DRAM controller. This makes open firmware implementations legally difficult.

Original Submission

SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture 13 comments

takyon writes:

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year's we've seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we've seen a lot of vendors make the switch from licensing Arm's architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on the ISA. While many vendors do choose to design their own microarchitectures to replace Arm-based microcontroller designs in their products, things get a little bit more complicated once you scale up in performance. It's here where SiFive comes into play as a RISC-V IP vendor offering more complex designs for companies to license – essentially a similar business model to Arm's – just that it's based on the new open ISA.
Today's announcement marks a milestone in SiFive's IP offering as the company is revealing its first ever out-of-order CPU microarchitecture, promising a significant performance jump over existing RISC-V cores, and offering competitive PPA metrics compared to Arm's products. [...] SiFive's design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. The A72 is quite an old comparison point by now, however SiFive's PPA targets are comparatively quite high, meaning the U8 should be quite competitive to Arm's latest generation cores.

Performance gains over previous designs are substantial:

The performance increases compared to previous generation SiFive cores are extremely impressive: Against a U54 at ISO-process, the new U84 features a 5.3x performance increase in SPECint2006. When taking into account the process node improvements that allow the U84 to clock higher, the generational increases that we'd be seeing in products will be more akin to a factor of 7.2x.
In terms of PPA, compared to a U7-series CPU, IPC increases come in at 2.3x resulting in 3.1x higher performance (ISO-process). A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.
On the same 7nm process, the U84 lands in at 0.28mm² per core and a cluster comprising four cores and a 2MB L2 cache measure in at 2.63mm². For comparison, an Arm Cortex-A55 as measured on the Kirin 980, also on 7nm, a core with its 128KB private L2 cache comes in at 0.36mm². Given that SiFive promises of similar performance to a Cortex-A72, which in turn would be more than double the performance of an A55, it looks like SiFive's U84 core would be extremely competitive in terms of its PPA.

Original Submission

GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)

takyon writes:

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.
The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.
GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.

2.5D/3D packaging.

Original Submission

SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs 12 comments

takyon writes:

SiFive has announced a mini-ITX motherboard with its SiFive Freedom U740:

At the heart of the SiFive board is a SiFive FU740 processor coupled with 8 GB DDR4 memory and 32 MB SPI Flash. It comes with a 4x USB 3.2 ports and a 16x PCIe expansion slot. The mini-ITX standard form factor makes it easy to build a RISC-V PC.
[...] SiFive Unmatched board will be available by Q4'20 for USD 665, and you can already register your interest. You will get a mini-ITX board, 32 GB MicroSD, and 3-meter CAT5e ethernet cable. SiFive did not speak on the commercial aspect of the product but are very confident about future development. Android and Chrome support is something we can see in the future. The product looks promising and we are excited to see future development in the RISC-V PC ecosystem.

Performance will probably be comparable to a Raspberry Pi 3. Alternatively:

PolarBerry is a Compact, Linux-capable RISC-V FPGA SBC and module (Crowdfunding)

Powered by Microchip PolarFire RISC-V SoC FPGA, PolarBerry is both a single board computer with Gigabit Ethernet and 40-pin GPIO header, as well as a system-on-module thanks to three Samtec board-to-board connectors.
[...] PolarBerry is not available just yet, but LinuxGizmos reports the SBC/SoM will be soon launched on Crowd Supply for $995 and shipments are expected to start in January 2021. Besides the aforementioned crowdfunding page, additional details may be found on the product page.

Previously: SiFive to Debut a RISC-V PC for Developers in October

Original Submission

Intel May Attempt to Acquire SiFive for $2 Billion 8 comments

takyon writes:

Intel (INTC) Reportedly Offers Over $2 Billion To Acquire the Fabless Semiconductor SiFive as the Consolidation Trend in the Industry Is Nowhere Close to Slowing Down

[According] to Bloomberg, Intel has reportedly offered over $2 billion to acquire the fabless semiconductor SiFive, a provider of commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.
Should this deal become a reality, it would mark the climax of growing bonhomie between Intel and SiFive. For instance, back in 2018, Intel was one of the participants in the Series C funding round of SiFive. Thereafter, in March 2021, SiFive announced a collaboration with the Intel Foundry Business (IFB) to develop innovative new RISC-V computing platforms.
Of course, unlike legacy Instruction Set Architectures (ISAs), RISC-V's proponents believe that it addresses the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, given that that the ISA is layered, extensible, and flexible. It is hardly surprising, therefore, that some believe RISC-V to be the future.
Bear in mind that SiFive was last valued at $500 million, as per the data available at PitchBook. This means that Intel would be paying a premium of over 300 percent relative to SiFive's 2020 valuation.

Previously: SiFive HiFive Unleashed Not as Open as Previously Thought
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
SiFive to Debut a RISC-V PC for Developers in October
SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs

Original Submission

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