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takyon writes:

Xilinx Announces Project Everest: The 7nm FPGA SoC Hybrid

This week Xilinx is making public its latest internal project for the next era of specialized computing. The new product line, called Project Everest in the interim, is based around what Xilinx is calling an ACAP – an Adaptive Compute Acceleration Platform. The idea here is that for both compute and acceleration, particularly in the data center, the hardware has to be as agile as the software. Project Everest will combine Xilinx's highest performing next-generation programmable logic along with application processors, real-time processors, programmable engines, RF, high-speed SerDes, programmable IO, HBM, and a custom network-on-chip. The idea is that space typically devoted to hard blocks in FPGAs (such as memory controllers) are now optimized on chip, leaving more programmable silicon for the compute and adaptability. Project Everest is one of the Three Big Trends as identified by Xilinx's new CEO, Victor Peng.

[...] Xilinx's ACAP portfolio will be initiated with TSMC's 7nm manufacturing process, with the first tapeouts due in late 2018. Xilinx states that Project Everest has been a monumental internal effort, taking 4-5 years and 1500 engineers already, with over $1b in R&D costs. The final big chips are expected to weigh in at 50 billion transistors, with a mix of monolithic and interposer designs based on configurations.

Today's announcement is more of a teaser than anything else – the diagram above is about the limit to which that Xilinx will talk about features and the product portfolio. The value of the ACAP, according to Xilinx, will be its feature set and millisecond-level configurability. For a server on the edge, for example, an ACAP can use both the programmable logic elements for millisecond bitstream reconfiguration of different processes along with the application processors for general logic or the programmable engines as ASIC-level acceleration. This can lead to, among other things, different AI acceleration techniques and 5G RF manageability by multiple containers/VMs on a single ACAP. The overriding idea is that the ACAP can apply dynamic optimization for workloads, with Xilinx citing a 10-100x speedup over CPUs and more use cases than GPUs or ASICs as a fundamental value to the new hardware, built through software and hardware programmability. Xilinx also stated that the RF will have four times the bandwidth of current 16nm radios, leveraging 16x16 800 MHz radios.

Also at The Register and The Next Platform.

Original Submission

An Anonymous Coward writes:

As part of the company's Supercomputing 2018, a new FPGA accelerator card was announced by Xilinx. The Xilinx Alveo U280 is one of the company's pre-ACAP 16nm UltraScale+ architecture FPGA products. The U280 features 8GB of Samsung High Bandwidth Memory (HBM2) plus 32GB of DDR4 memory. The goal of the new card is to accelerate database search and analytics, machine learning inference, and other memory-bound applications.

Buried in the documentation for the card is a nugget of extremely interesting information:

"The U280 acceleration card includes CCIX support to leverage existing server interconnect infrastructure for high bandwidth, low latency cache coherent shared memory access with CCIX enabled processors including Arm and AMD." (Source: Xilinx Alveo U280 whitepaper WP50 (v1.0) accessed 16 November 2018)

We were recently at the AMD Next Horizon Event and STH friend Dr. Ian Dr. Ian Cutress at Anandtech (not a typo, that is what his SC18 badge said) touched upon this in his interview with AMD CTO Mark Papermaster. Neither in the Rome disclosure nor the interview did AMD confirm CCIX support. However, AMD publicly supports CCIX and Gen-Z and when we asked if this means Rome supports CCIX all we received was that AMD supports CCIX but has not announced a product with it yet. Arm may have chips derived from its IP with CCIX support, but AMD has a more well-defined roadmap.

https://www.servethehome.com/xilinx-alveo-u280-launched-possibly-with-amd-epyc-ccix-support/

Original Submission

takyon writes:

AMD in $35 Billion All-Stock Acquisition of Xilinx

After a couple of weeks of rumor, as well as a couple of years of hearsay, AMD has gone feet first into a full acquisition of FPGA manufacturer Xilinx. The deal involves an all-stock transaction, leveraging AMD's sizeable share price in order to enable an equivalent $143 per Xilinx share – current AMD stockholders will still own 74% of the combined company, while Xilinx stockholders will own 26%. The combined $135 billion entity will total 13000 engineers, and expand AMD's total addressable market to $110 Billion. It is believed that the key reasons for the acquisition lie in Xilinx's adaptive computing solutions for the data center market.

[...] As part of the acquisition, Victor Peng will join AMD as president responsible for the Xilinx business, and at least two Xilinx directors will join the AMD Board of Directors upon closing.

Part of the enablement of the acquisition is AMD leveraging its market capitalization of ~$100 billion, and a lot of the industry will draw parallels of Intel's acquisition of FPGA-manufacturer Altera in December 2015 for $16.7 billion. The high-performance FPGA markets, as well as SmartNICs, adaptive SoCs, and other controllable logic, reside naturally in the data center markets more than most other markets. With AMD's recent growth in the enterprise space with its Zen-based EPYC processor lines, a natural evolution one might conclude would be synergizing high-performance compute with adaptable logic under one roof, which is precisely the conclusion that Intel also came to several years ago. AMD reported last quarter that it had broken above the 10% market share in Enterprise with its EPYC product lines, and today's earnings call is also expected to see growth. AMD is already reporting revenue up +56% year on year company-wide, with +116% in the Enterprise, Embedded, and Semi-Custom markets.

Also at The Register, Phoronix, and Wccftech.

Previously: AMD Negotiating to Acquire Xilinx

Original Submission