Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Thursday October 22 2020, @11:39PM   Printer-friendly
from the moving-a-bit-faster dept.

Silicon Motion Launches PCIe 4.0 NVMe SSD Controllers

Silicon Motion has announced the official launch of their first generation of PCIe 4.0-capable NVMe SSD controllers. These controllers have been on the roadmap for quite a while and have been previewed at trade shows, but the first models are now shipping. The high-end SM2264 and mainstream SM2267/SM2267XT controllers will enable consumer SSDs that move beyond the performance limits of the PCIe 3.0 x4 interface that has been the standard for almost all previous consumer NVMe SSDs.

The high-end SM2264 controller is the successor to Silicon Motion's SM2262(EN) controllers, and the SM2264 brings the most significant changes that add up to a doubling of performance. The SM2264 still uses 8 NAND channels, but now supporting double the speed: up to 1600MT/s. The controller includes four ARM Cortex R8 cores, compared to two cores on SMI's previous client/consumer NVMe controllers. As with most SSD controllers aiming for the high end PCIe 4.0 product segment, the SM2264 is fabbed on a smaller node: TSMC's 12nm FinFET process, which allows for substantially better power efficiency than the 28nm planar process used by the preceding generation of SSD controllers. The SM2264 also includes support for some enterprise-oriented features like SR-IOV virtualization, though we probably won't see that enabled on consumer SSD products. The SM2264 also includes the latest generation of Silicon Motion's NANDXtend ECC system, which switches from a 2kb to 4kB codeword size for the LDPC error correction.

Also at Guru3D.

Related: Silicon Motion Controller to Enable High Speed, Low Cost Portable USB SSDs


Original Submission

Related Stories

Silicon Motion Controller to Enable High Speed, Low Cost Portable USB SSDs 12 comments

A USB Stick as an SSD? A New Silicon Motion SM3282 Single-Chip Controller for USB SSDs

Silicon Motion has introduced its first single-chip controller for portable USB SSDs. The SM3282 promises to enable makers of portable drives to offer up to 400 MB/s sequential read speeds in a cost-efficient manner previously unachievable by external SSDs.

[...] Previously, makers of external SSDs had to use a USB-to-PCIe bridge alongside an SSD controller to build their products, which greatly increased BOM costs as well as the final price. The SM3282 packs all the necessary functionality into a single chip and thus reduces BOM cost of external SSDs.

SSD - Solid State Drive
BOM - Bill of Materials


Original Submission

Marvell Announces PCIe 5.0 SSD Controllers Capable of 14 GB/s Sequential Reads 10 comments

Marvell Announces First PCIe 5.0 NVMe SSD Controllers: Up To 14 GB/s

Today Marvell is announcing the first NVMe SSD controllers to support PCIe 5.0, and a new branding strategy for Marvell's storage controllers. The new SSD controllers are the first under the umbrella of Marvell's Bravera brand, which will also encompass HDD controllers and other storage accelerator products. The Bravera SC5 family of PCIe 5.0 SSD controllers will consist of two controller models: the 8-channel MV-SS1331 and the 16-channel MV-SS1333.

These new SSD controllers roughly double the performance available from PCIe 4.0 SSDs, meaning sequential read throughput hits 14 GB/s and random read performance of around 2M IOPS. To reach this level of performance while staying within the power and thermal limits of common enterprise SSD form factors, Marvell has had to improve power efficiency by 40% over their previous generation SSD controllers. That goes beyond the improvement that can be gained simply from smaller fab process nodes, so Marvell has had to significantly alter the architecture of their controllers. The Bravera SC5 controllers still include a mix of Arm cores (Cortex-R8, Cortex-M7 and a Cortex-M3), but now includes much more fixed-function hardware to handle the basic tasks of the controller with high throughput and consistently low latency.

Top-of-the-line PCIe 4.0 controllers from Phison and Silicon Motion are capable of 7.4 GB/s of sequential reads.

Related: Marvell Looking to Integrate Machine Learning Engines Onto SSD Controllers
Marvell Announces ThunderX3, an ARM Server CPU With 96 Cores, 384 Threads
Marvell ThunderX3 ARM Server CPU Will Have Up to 60 Cores Per Die, with 96-Core Dual-Die Option
Silicon Motion Launches PCIe 4.0 NVMe SSD Controllers


Original Submission

This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
(1)
  • (Score: 0) by Anonymous Coward on Friday October 23 2020, @12:51AM

    by Anonymous Coward on Friday October 23 2020, @12:51AM (#1067749)

    I want the same on the end of usb3/c. With Ethernet 1Gb and WiFi ac or better. I need a fast backup when working at my desk, but would like to walk away by pulling the usb and it seamlessly switch over to WiFi then sit at my desk and plug back in and we connects back to the faster interface. Running a full backup or mass data motion continuously without an interruption.

    Then I be impressed

  • (Score: 0) by Anonymous Coward on Friday October 23 2020, @01:08AM (4 children)

    by Anonymous Coward on Friday October 23 2020, @01:08AM (#1067752)

    Tell us what "sillicon motion" is about.

    • (Score: 3, Informative) by takyon on Friday October 23 2020, @01:21AM (3 children)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday October 23 2020, @01:21AM (#1067755) Journal

      Company that makes the controllers for cheap SSDs.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 2) by krishnoid on Friday October 23 2020, @01:47AM (2 children)

        by krishnoid (1156) on Friday October 23 2020, @01:47AM (#1067761)

        And "controller"?

        • (Score: 3, Informative) by takyon on Friday October 23 2020, @01:53AM

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday October 23 2020, @01:53AM (#1067764) Journal

          A computer that manages the SSD.

          https://en.wikipedia.org/wiki/Flash_memory_controller [wikipedia.org]

          A flash memory controller (or flash controller) manages data stored on flash memory and communicates with a computer or electronic device. Flash memory controllers can be designed for operating in low duty-cycle environments like SD cards, CompactFlash cards, or other similar media for use in digital cameras, PDAs, mobile phones, etc. USB flash drives use flash memory controllers designed to communicate with personal computers through the USB port at a low duty-cycle. Flash controllers can also be designed for higher duty-cycle environments like solid-state drives (SSD) used as data storage for laptop computer systems clear up to mission-critical enterprise storage arrays.

          --
          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
        • (Score: 0) by Anonymous Coward on Friday October 23 2020, @01:53AM

          by Anonymous Coward on Friday October 23 2020, @01:53AM (#1067765)

          computer that “sits” on the drive to improve processing throughput and manage space usage. Can even rotate sector for prevent burn in.

  • (Score: 2) by jasassin on Friday October 23 2020, @02:38AM (3 children)

    by jasassin (3566) <jasassin@gmail.com> on Friday October 23 2020, @02:38AM (#1067773) Homepage Journal

    I read most drives run on PCI Express 3.0 x4 3.940GB/s.

    PCI Express 4.0 x4 will be 7.880GB/s.

    Are there drives maxing the 3.9GB/s? Next question, how fast will PCI Express 4.0 drives be? Anything close to 7.8GB/s.

    --
    jasassin@gmail.com GPG Key ID: 0xE6462C68A9A3DB5A
  • (Score: 0) by Anonymous Coward on Friday October 23 2020, @01:25PM (1 child)

    by Anonymous Coward on Friday October 23 2020, @01:25PM (#1067859)

    good thing we are reaching the end of moores law AND periphale slots (pcie, usb, etc) are still a thing.
    there's nothing a manufacturer, say like apple, would like more then printing a huge postage stamp that includes everything: cpu, ram, storage, grafics, sensors (gps, accel., etc).
    this way if even just one element breaks and you need it, you can't replace it, (like you can if you have expansion slots) and have to add it to the landfill and buy new!
    it's supposedly getting more difficult to print chips that are 100 percent okay (thus binning is a thing) and this will require to print seperate chips with a interconnect (a open one being a expansion slot) thus preventing slightly spoiled fruit from filling up holes in the ground ...
    rant: it is beyond me why a perfectly working iPad needs to be destroyed just because the component that is arguably the most primitif, e.g. battery, is broken. 100 years ago sailors would have hang you if you had to throw away your gps navigation device just because the battery ... died.

    • (Score: 3, Informative) by takyon on Saturday October 24 2020, @12:39AM

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Saturday October 24 2020, @12:39AM (#1068125) Journal

      Having large amounts of L4 cache near the CPU, or even microns away from the CPU, is going to be one of the major ways to improve performance going forward. It will be unavoidable. But you could still have a large pool of DRAM in DIMMs further away from the CPU. DRAM on die should not be shortening the life of the CPU to a noticeable extent.

      Apple is already pretty much there. They are expanding their ARM SoCs towards their desktop/workstation product lines. They may try to pair discrete GPUs with some of their ARM SoCs for a while, beats me.

      Chiplets on interposers are countering yield problems. Small chiplets get great yields and reduce costs. Newer interposer/interconnect technologies minimize the performance impact. AMD can make a tiny 8-core chiplet (will get smaller or grow core count by the "5nm" or "3nm" node), which is a lot for most users in the first place, and you generally won't notice the impact of a second 8-core chiplet introducing more latency. Nvidia, Intel, and AMD are all moving towards some kind of chiplet/multi-chip module design for GPUs.

      The "slightly spoiled fruit" of binning/disabled cores is of no consequence to most people. If you get a product with 1-2 6-core chiplets with 2 cores disabled on each, it's going to work just fine.

      Non-removable batteries are a nuisance. But the device can continue to have a life as long as you can commit towards plugging it in forever. For example, mount an iPad with dead battery on a wall near an outlet, always plugged in. Or put it on a kickstand somewhere and use it like an Echo Show.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(1)