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posted by martyb on Friday June 11, @06:02AM   Printer-friendly [Skip to comment(s)]
from the if-you-can't-beat-'em,-buy-'em? dept.

Intel (INTC) Reportedly Offers Over $2 Billion To Acquire the Fabless Semiconductor SiFive as the Consolidation Trend in the Industry Is Nowhere Close to Slowing Down

[According] to Bloomberg, Intel has reportedly offered over $2 billion to acquire the fabless semiconductor SiFive, a provider of commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.

Should this deal become a reality, it would mark the climax of growing bonhomie between Intel and SiFive. For instance, back in 2018, Intel was one of the participants in the Series C funding round of SiFive. Thereafter, in March 2021, SiFive announced a collaboration with the Intel Foundry Business (IFB) to develop innovative new RISC-V computing platforms.

Of course, unlike legacy Instruction Set Architectures (ISAs), RISC-V's proponents believe that it addresses the skyrocketing cost of designing and manufacturing increasingly complex new chip architectures, given that that the ISA is layered, extensible, and flexible. It is hardly surprising, therefore, that some believe RISC-V to be the future.

Bear in mind that SiFive was last valued at $500 million, as per the data available at PitchBook. This means that Intel would be paying a premium of over 300 percent relative to SiFive's 2020 valuation.

Previously: SiFive HiFive Unleashed Not as Open as Previously Thought
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)
SiFive to Debut a RISC-V PC for Developers in October
SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs

Original Submission

Related Stories

SiFive HiFive Unleashed Not as Open as Previously Thought 17 comments

Spotted over on Phoronix:

While free software/hardware advocates have been ecstatic about the RISC-V open-source, royalty-free processor architecture, hardware so far hasn't been as open as desired.

While this processor ISA is entirely open and living up to its merits, it turns out the RISC-V implementations so far haven't been quite as open as one would have thought. A Phoronix reader pointed out to us some remarks by developers on the main RISC-V development board out so far, the SiFive HiFive Unleashed

Ron Minnich who has run the Coreboot project for more than the past decade and spearheads the effort of getting Coreboot on new Chrome OS devices at Google, commented on the Unleashed development board this weekend:

All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive.

Open instruction sets do not necessarily result in open implementations. An open implementation of RISC-V will require a commitment on the part of a company to opening it up at all levels, not just the instruction set.

The issue stems from the use of third party IP used to complete the SoC as Risc-V is an instruction set, not a physical hardware design. The actual silicon of the CPU must be designed in order to implement the instruction set as actual hardware and glue logic to tie the CPU to other hardware like memory and bus controllers. In the case, the HiFive Unleashed features a DRAM controller from Cadence which uses a proprietary binary blob to initialize the DRAM controller. This makes open firmware implementations legally difficult.

Original Submission

Qualcomm Invests in RISC-V Startup SiFive 4 comments

Qualcomm Invests in RISC-V Startup SiFive

Investors are zeroing in on the open standard RISC-V instruction set architecture and the processor intellectual property being developed by a batch of high-flying chip startups.

Last fall, Esperanto Technologies announced a $58 million funding round. The chip IP vendor is incorporating more than 1,000 RISC-V cores onto a single 7-nm chip. Data storage specialist Western Digital is an early investor in Esperanto, Mountain View, Calif.

This week, another RISC-V startup, SiFive, announced a $65.4 million funding round that included new investor Qualcomm Ventures. SiFive, San Mateo, Calif., has so far raised more than $125 million, and is seen as a challenger to chip IP leader Arm.

Observers note that wireless modem leader Qualcomm is among Arm's biggest customers, making its investment in SiFive intriguing. Also participating in the Series D round were existing investors Chengwei Capital of Shanghai along with Sutter Hill Ventures and Spark Capital. Intel Capital and Western Digital also were early investors.

Also at EE Times.

See also: SiFive Acquires USB 2.0 and 3.x IP Portfolio to Strengthen RISC-V SoCs

Previously: RISC-V Projects to Collaborate
SiFive and UltraSoC Partner to Accelerate RISC-V Development Through DesignShare
SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
Linux Foundation and RISC-V Proponents Launch CHIPS Alliance

Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.

Esperanto Technologies and SiFive look like the names to watch.

Related: First Open Source RISC-V Implementations Become Available
Western Digital Unveils RISC-V Controller Design
Raspberry Pi Foundation Announces RISC-V Foundation Membership
Western Digital Publishes RISC-V "SweRV" Core Design Under Apache 2.0 License

Original Submission

SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture 13 comments

SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP

In the last few year's we've seen an increasing amount of talk about RISC-V and it becoming real competitor to the Arm in the embedded market. Indeed, we've seen a lot of vendors make the switch from licensing Arm's architecture and IP designs to the open-source RISC-V architecture and either licensed or custom-made IP based on the ISA. While many vendors do choose to design their own microarchitectures to replace Arm-based microcontroller designs in their products, things get a little bit more complicated once you scale up in performance. It's here where SiFive comes into play as a RISC-V IP vendor offering more complex designs for companies to license – essentially a similar business model to Arm's – just that it's based on the new open ISA.

Today's announcement marks a milestone in SiFive's IP offering as the company is revealing its first ever out-of-order CPU microarchitecture, promising a significant performance jump over existing RISC-V cores, and offering competitive PPA metrics compared to Arm's products. [...] SiFive's design goals for the U8-Series are quite straightforward: Compared to an Arm Cortex-A72, the U8-Series aims to be comparable in performance, while offering 1.5x better power efficiency at the same time as using half the area. The A72 is quite an old comparison point by now, however SiFive's PPA targets are comparatively quite high, meaning the U8 should be quite competitive to Arm's latest generation cores.

Performance gains over previous designs are substantial:

The performance increases compared to previous generation SiFive cores are extremely impressive: Against a U54 at ISO-process, the new U84 features a 5.3x performance increase in SPECint2006. When taking into account the process node improvements that allow the U84 to clock higher, the generational increases that we'd be seeing in products will be more akin to a factor of 7.2x.

In terms of PPA, compared to a U7-series CPU, IPC increases come in at 2.3x resulting in 3.1x higher performance (ISO-process). A lot of the performance increases of the U8-series come thanks to the increased frequencies capabilities which are 1.4x higher this generation, with the core scaling up to 2.6GHz on 7nm.

On the same 7nm process, the U84 lands in at 0.28mm² per core and a cluster comprising four cores and a 2MB L2 cache measure in at 2.63mm². For comparison, an Arm Cortex-A55 as measured on the Kirin 980, also on 7nm, a core with its 128KB private L2 cache comes in at 0.36mm². Given that SiFive promises of similar performance to a Cortex-A72, which in turn would be more than double the performance of an A55, it looks like SiFive's U84 core would be extremely competitive in terms of its PPA.

Related: Qualcomm Invests in RISC-V Startup SiFive

Original Submission

GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+

GlobalFoundries and SiFive announced on Tuesday that they will be co-developing an implementation of HBM2E memory for GloFo's 12LP and 12LP+ FinFET process technologies. The IP package will enable SoC designers to quickly integrate HBM2E support into designs for chips that need significant amounts of bandwidth.

The HBM2E implementation by GlobalFoundries and SiFive includes the 2.5D packaging (interposer) designed by GF, with the HBM2E interface developed by SiFive. In addition to HBM2E technology, licensees of SiFive also gain access to the company's RISC-V portfolio and DesignShare IP ecosystem for GlobalFoundries' 12LP/12LP+, which will enable SoC developers to build RISC-V-based devices [using] GloFo's advanced fab technology.

GlobalFoundries and SiFive suggest that the 12LP+ manufacturing process and the HBM2E implementation will be primarily used for artificial intelligence training and inference applications for edge computing, with vendors looking to optimize for TOPS-per-milliwatt performance.

2.5D/3D packaging.

Related: Samsung Announces "Flashbolt" HBM2E (High Bandwidth Memory) DRAM packages
SK Hynix Announces HBM2E Memory for 2020 Release
GlobalFoundries Develops "12LP+" Fabrication Process
Qualcomm Invests in RISC-V Startup SiFive
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture

Original Submission

SiFive to Debut a RISC-V PC for Developers in October 9 comments

SiFive to Debut RISC-V PC for Developers based on Freedom U740 next-gen SoC

In recent years, people have discussed the need to have Arm-based PCs or workstations for developers to work directly on the target hardware, and there are now several options including SynQuacer E-Series 24-Core Arm PC, Ampere eMAG 64bit Arm Workstation, and HoneyComb LX2K 16-core Arm Workstation.

Now it appears we'll soon get something similar for RISC-V architecture with SiFive to debut the first RISC-V PC for developers at the Linley Fall Processor Conference 2020 taking place on October 20-22 and October 27-29. The PC will be powered by Freedom U740 next-generation RISC-V processor that will also be introduced at the event.

We have very few details about this point in time, but the company points the SiFive Freedom U740 (FU740) SoC will enable professional developers to create RISC-V applications from bare-metal to Linux-based. The processor is said to combines[sic] a heterogeneous mix+match core complex with modern PC expansion capabilities, which probably means PCIe, SATA etc.., and the company will provide tools to ease professional software development.

Freedom U740 details are unknown, but Freedom U540 is a quad-core CPU that was used in the HiFive Unleashed single-board computer.

Related: SiFive Introduces RISC-V Linux-Capable Multicore Processor
SiFive HiFive Unleashed Not as Open as Previously Thought
SiFive Announces a RISC-V Core With an Out-of-Order Microarchitecture
GlobalFoundries and SiFive Partner on High Bandwidth Memory (HBM2E)

Original Submission

SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs 12 comments

SiFive has announced a mini-ITX motherboard with its SiFive Freedom U740:

At the heart of the SiFive board is a SiFive FU740 processor coupled with 8 GB DDR4 memory and 32 MB SPI Flash. It comes with a 4x USB 3.2 ports and a 16x PCIe expansion slot. The mini-ITX standard form factor makes it easy to build a RISC-V PC.

[...] SiFive Unmatched board will be available by Q4'20 for USD 665, and you can already register your interest. You will get a mini-ITX board, 32 GB MicroSD, and 3-meter CAT5e ethernet cable. SiFive did not speak on the commercial aspect of the product but are very confident about future development. Android and Chrome support is something we can see in the future. The product looks promising and we are excited to see future development in the RISC-V PC ecosystem.

Performance will probably be comparable to a Raspberry Pi 3. Alternatively:

PolarBerry is a Compact, Linux-capable RISC-V FPGA SBC and module (Crowdfunding)

Powered by Microchip PolarFire RISC-V SoC FPGA, PolarBerry is both a single board computer with Gigabit Ethernet and 40-pin GPIO header, as well as a system-on-module thanks to three Samtec board-to-board connectors.

[...] PolarBerry is not available just yet, but LinuxGizmos reports the SBC/SoM will be soon launched on Crowd Supply for $995 and shipments are expected to start in January 2021. Besides the aforementioned crowdfunding page, additional details may be found on the product page.

See also: SiFive Is Launching The Most Compelling RISC-V Development Board Yet

Previously: SiFive to Debut a RISC-V PC for Developers in October

Original Submission

Intel Will License SiFive's New P550 RISC-V Core 18 comments

Intel to make a custom SiFive-based RISC-V CPU, will be fabricated on a 7 nm node in a first step towards competing directly with Arm-based chips

The partnership will see Intel license SiFive's IP to create its own SiFive P550-based 64-bit SoC that it will fabricate on its new 7 nm node. It will form the basis of a new development platform Intel is calling Horse Creek, and will be made available to customers interested in exploring its potential in various applications involving embedded SoC tech. This could mean smartphones, but also cars, IoT products and the like. If Intel gets enough interest, it could take the relationship further. Intel hasn't yet revealed the technical specifications of the SoC, so we don't know whether it will be a single-core or multi-core platform, although the latter is likely. It's GPU tech is also unknown at this time, but Xe-based graphics are likely.

While the first Horse Creek SoCs will be ready next year, it isn't likely we will see any Intel RISC-V-based chips in commercially available products until 2023 at least.

SiFive recently announced two new high-performance 64-bit RISC-V cores, the Performance P550 and Performance P270:

SiFive compares the Performance P550 core to Arm's Cortex-A75 with higher performance in SPECint2006 and SPECfp2006 integer/floating-point benchmark, all [in] a much smaller area which would enable a quad-core P550 cluster on about the same footprint as a single Cortex-A75 core.

See also: Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards

Previously: Intel May Attempt to Acquire SiFive for $2 Billion

Original Submission

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  • (Score: 3, Interesting) by venn on Friday June 11, @08:05AM (5 children)

    by venn (13224) on Friday June 11, @08:05AM (#1144200)

    Could this be a sign that x86 is nearing its end? Or is it an embrace, extend, and extinguish strategy.

    • (Score: 2, Interesting) by Anonymous Coward on Friday June 11, @08:33AM

      by Anonymous Coward on Friday June 11, @08:33AM (#1144201)

      I'd much rather see Intel sunset than x86. The problems with x86 are fixable, as AMD demonstrated with their 64-bit extensions. The Intel company culture is not.

    • (Score: 5, Informative) by FatPhil on Friday June 11, @11:27AM

      Intel bought into ARM ages ago, and killed (their bit of) that.

      I wouldn't expect this to be anything apart from an attempt to weaken Risc-V.
      I know I'm God, because every time I pray to him, I find I'm talking to myself.
    • (Score: 1, Interesting) by Anonymous Coward on Friday June 11, @02:51PM (1 child)

      by Anonymous Coward on Friday June 11, @02:51PM (#1144252)

      RISC V is not a real threat to x86 for many years, and by then it will be obsolete. Flexible architectures are where all the focus is.

      • (Score: 0) by Anonymous Coward on Friday June 11, @06:48PM

        by Anonymous Coward on Friday June 11, @06:48PM (#1144342)

        the (sane) "consumer" should like intel. the stuff is backwards compatible.
        the producer prefers ARM, 'cause ARM license is easy to get and you can modify to their ..wallets ..err... hearts desire ... mostly so new software doesn't run on old hardware (why do you think you need a new "secure" smart phone every 3 years?)

        intel could not do that (w/ x86) 'cause elephant in room already and would have given much anti-trust ammo if they would have done like ARM.

        we can just hope (!) that this good part of intel (shit that runs on iCore runs on pentium etc etc) bleeds into the RISC V domain (sans the m$ dog-pooh-smell-on the-shoesole).
        we can hope, that is all ...

    • (Score: -1, Troll) by Anonymous Coward on Friday June 11, @06:40PM

      by Anonymous Coward on Friday June 11, @06:40PM (#1144337)

      It's more likely that Intel, being Jew-run, is finding out that designing and making chips is a lot more difficult than buying IP and suing others in the East District of Texas. You just wait, you'll see I was right.

  • (Score: 0) by Anonymous Coward on Friday June 11, @05:11PM (1 child)

    by Anonymous Coward on Friday June 11, @05:11PM (#1144299)

    I understand that Moore's Law has been used as a business plan, almost since it was stated -- you must increase device density (reduce transistor size) to stay competitive.

    However, it seems like some relatively simple chips are now so cheap that perhaps there is reasonable business to be had without pushing on the latest and greatest high density technology. I'm thinking of things like calculators, small ECUs in cars that run the windshield wipers or windows, or even the processor in a basic microwave oven.

    Are there fabs that are working to reduce the total delivered cost of this type of system on chip, without reducing line widths any further? Or does the cost of silicon so dominate the cost of the final product that going smaller still wins, even in this "commodity" part of the market?