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posted by martyb on Friday August 27 2021, @08:10PM   Printer-friendly

Imagination Technologies to design RISC-V cores:

Now better known for its PowerVR embedded GPUs, Imagination Technologies tried to enter the CPU market by purchasing MIPS Technologies and introducing microAptiv, interAptiv, and proAptiv cores in 2012.

It did not end up well, as the company had to sell its MIPS technology a few years later, and the MIPS architecture is now barely supported. But Imagination is now working on getting back into the CPU space by designing RISC-V cores.

[...] a May 2021 report by the Financial Times claims Imagination expects to invest up to $150m over the next two years to target a fresh push into the processor design market, specifically citing the RISC-V architecture.

Press release.

Also at Tom's Hardware.

See also: QEMU 6.1 Released With RISC-V Improvements, AMD Emulation Fixes

Related: Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off
Wave Computing Acquires MIPS Technologies
Imagination Announces B-Series GPU IP: Scaling up with Multi-GPU


Original Submission

Related Stories

Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off 9 comments

The company that failed to acquire Lattice Semiconductor will acquire Imagination Technologies instead:

https://www.bloomberg.com/news/articles/2017-09-22/imagination-technologies-agrees-to-takeover-by-canyon-bridge

Imagination Technologies Group Plc agreed to be acquired by China-backed private equity firm Canyon Bridge Capital Partners.

Canyon Bridge said it will pay 182 pence a share in cash, or more than 500 million pounds ($675 million), for the U.K. designer of graphics chips. That's 42 percent more than Imagination's closing share price on Friday.

As part of the deal, Imagination will sell its U.S.-based embedded processor unit MIPS to Tallwood MIPS, a company indirectly owned by California-based investment firm Tallwood Venture Capital, Canyon Bridge said.

Canyon Bridge was keen to structure a bid to avoid scrutiny from U.S. regulators, Bloomberg reported earlier this month.

Earlier in September President Donald Trump rejected a takeover by Canyon Bridge of U.S. chipmaker Lattice Semiconductor Corp., just the fourth time in a quarter century that a U.S. president has ordered a foreign sale of an American firm stopped for security reasons.

Also at The Verge, AnandTech, and Financial Times.

Previously:

Related:


Original Submission

Wave Computing Acquires MIPS Technologies 16 comments

Submitted via IRC for takyon

Wave Computing today announced that it has acquired MIPS Tech, Inc. (formerly MIPS Technologies), a global leader in RISC processor Intellectual Property (IP) and licensable CPU cores. The acquisition will accelerate Wave's strategy of offering AI acceleration from the Datacenter to the Edge of Cloud by extending the company's products beyond AI systems to now also include AI-enabled embedded solutions.

[...] For example, Datacenter-centric AI applications today need many weeks to train using coprocessors such as GPUs, only to require a different architecture for inferencing at the Edge. The lack of a common AI platform, from Datacenter to Edge, slows market growth and reduces productivity of data scientists in fields such as autonomously driven vehicles, IoT sensors and more.

[...] "Wave's integration of two industry-leading compute architectures in a single data plane/control plane solution – Dataflow and Von Neumann – will be truly unique and an industry-first. It will fuel new, ground-breaking innovations in AI and other fields."

MIPS architecture.

Source: Wave Computing Acquires MIPS Technologies

Related: Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off
Wave Computing and Others Adopt 64-Bit MIPS Cores


Original Submission

Imagination Announces B-Series GPU IP: Scaling up with Multi-GPU 3 comments

Imagination has announced new B-series GPU designs focused on automotive and high-performance computing use cases, as it has become difficult for the company to compete in the mobile GPU market:

It's almost been a year since Imagination had announced its brand-new A-series GPU IP, a release which at the time the company called its most important in 15 years. The new architecture indeed marked some significant updates to the company's GPU IP, promising major uplifts in performance and promises of great competitiveness. Since then, other than a slew of internal scandals, we've heard very little from the company – until today's announcement of the new next-generation of IP: the B-Series.

The new Imagination B-Series is an evolution of last year's A-Series GPU IP release, further iterating through microarchitectural improvements, but most importantly, scaling the architecture up to higher performance levels through a brand-new multi-GPU system, as well as the introduction of a new functional safety class of IP in the form of the BXS series.

[....] Imagination's current highest-end hardware implementation in the BXT series is the BXT 32-1024, and putting four of these together creates an MC4 GPU. In a high-performance implementation reaching up to 1.5GHz clock speeds, this configuration would offer up to 6TFLOPs of FP32 computing power. Whilst this isn't quite enough to catch up to Nvidia and AMD, it's a major leap for a third-party GPU IP provider that's been mostly active in the mobile space for the last 15 years.

[....] Beyond the addition of safety critical features on the BXS series, the automotive IP also features some specific enhancements in the microarchitecture that allows for better performance scaling for workloads that are more unique to the automotive space. One such aspect is geometry, where automotive vendors have the tendency to use absurd amounts of triangles. Imagination says they've tweaked their designs to cover these more demanding use-cases, and together with some MSAA specific optimisations they can reach up to a 60% greater performance for these automotive edge-cases, compared to the regular non-automotive IP.

Related: Imagination Technologies Group Up for Sale


Original Submission

Imagination Technologies Announces "Catapult" RISC-V CPU Cores 17 comments

Imagination introduces Catapult RISC-V CPU cores

As expected, Imagination Technologies is giving another try to the CPU IP market with the Catapult RISC-V CPU cores following their previous unsuccessful attempt with the MIPS architecture, notably the Aptiv family.

Catapult RISC-V CPUs are/will be available in four distinct families for dynamic microcontrollers, real-time embedded CPUs, high-performance application CPUs, and functionally safe automotive CPUs.

The new 32-/64-bit RISC-V cores will be scalable to up to eight asymmetric coherent cores-per cluster, offer a "plethora of customer configurable options", and support optional custom accelerators. What you won't see today are block diagrams and detailed technical information about the cores because apparently, all that information is confidential even though some Catapult RISC-V cores are already shipping "in high-performance Imagination automotive GPUs". The only way to get more details today is to sign an NDA.

Also at AnandTech and Phoronix.

Previously: Imagination Announces B-Series GPU IP: Scaling up with Multi-GPU
Imagination Technologies Plans to Design RISC-V Cores

Related: Innosilicon Graphics Cards Based on "Fantasy One" GPU Feature Up to 32GB GDDR6X Memory


Original Submission

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  • (Score: 3, Interesting) by DannyB on Friday August 27 2021, @08:46PM (4 children)

    by DannyB (5839) Subscriber Badge on Friday August 27 2021, @08:46PM (#1171532) Journal

    I am personally hopeful that RISC-V will attract development efforts to build chips for everything from the smallest of microcontrollers to the biggest of fire breathing servers, and everything in between.

    It's not that the various chip designs will be open (I'm sure they won't be). It's that the industry might gradually standardize on something that doesn't have Intel's decades of horrible baggage. Something clean and simple. Something that the smallest implementation can be built on breadboards. (Sorry don't have link handy)

    I remember back in the 80's in a Mac vs PC discussion, someone saying it would be good to have one single standard. (Meaning PC compatible) Yes, it would. But it would be better to have a really good standard. Starting with ISA. Then standard OS (Linux). And maybe a few common UIs.

    I would be amused if I live to see that become something like the ultimate endpoint.

    But, there are some other OSes on the horizon that could end up betting better than Linux. (And you should never begin or end a sentence with either But or And.)

    --
    If you think a fertilized egg is a child but an immigrant child is not, please don't pretend your concerns are religious
    • (Score: 2) by DannyB on Friday August 27 2021, @08:48PM

      by DannyB (5839) Subscriber Badge on Friday August 27 2021, @08:48PM (#1171534) Journal

      s/betting/being/g

      --
      If you think a fertilized egg is a child but an immigrant child is not, please don't pretend your concerns are religious
    • (Score: 3, Insightful) by takyon on Friday August 27 2021, @09:16PM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday August 27 2021, @09:16PM (#1171540) Journal

      RISC-V vs. ARM will be more interesting than RISC-V vs. x86. x86 just works, whereas the ARM ecosystem is fragmented. RISC-V could replace ARM, only to face the same problems.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 2, Insightful) by Anonymous Coward on Saturday August 28 2021, @05:56AM

      by Anonymous Coward on Saturday August 28 2021, @05:56AM (#1171665)

      If God said "it would be nice to have one standard life form"
      If Linus had said "it would be nice to have one kernel"

      Think before you puke. I want my CPUs in all flavors just like Ice Cream.
      Some flavors die on introduction, some fade away, some cruse thru life just being Vanilla.

      Oh you can swap God with what ever you want. Or you can get flippy about it. your choice.

    • (Score: 2, Interesting) by NPC-131072 on Saturday August 28 2021, @03:28PM

      by NPC-131072 (7144) on Saturday August 28 2021, @03:28PM (#1171774) Journal

      Something that the smallest implementation can be built on breadboards.

      Or as a pixel shader. [pimaker.at]

  • (Score: 4, Interesting) by Snotnose on Friday August 27 2021, @09:31PM (3 children)

    by Snotnose (1623) on Friday August 27 2021, @09:31PM (#1171542)

    Back around 2000 my job was to certify CPUs for Microsoft. I don't remember the exact details, but Microsoft had a set of code I could minimally change to prove a CPU could run Microsoft code.

    x86? Never saw it

    SH-4? Minor issues but not a big deal.

    MIPS? If memory serves they reserved the upper 25% of memory for I/O. In other words, if you went above 0xd000000000 (I hope I got that right) then you were doing I/O, not memory. The Microsoft test wanted 100% of the 32 bit memory space to be memory.

    I contacted the Microsoft guy who wrote the tests, his attitude was pretty much "thems the specs, deal". I couldn't deal, I had no say on the hardware. The hardware wasn't going to pass, the hardware vendor wanted it to pass, Microsoft was pretty much "tell him I'm at lunch".

    Keep in mind back in 2000 Microsoft was approving CPUs for WinCe, which is the most accidentally appropriate name for an OS I've ever run across. Back then having a full 32 bit addressing space for an embedded system was not going to happen. Plus, WinCE. A horrible RTOS that showed Microsoft had no clue what a RTOS was. Where do I start?

    1) How much stack space does each process need? Dunno.
    2) What is the Interrupt latency? Dunno
    3) How much RAM does each process need? Dunno
    4) When will process X get to run? Dunno

    In other words, calling WinCE an RTOS was a joke. And as it turned out, reserving 25% of your addressing space for I/O also turned out to be a fail. But, somehow, I got the MIPS approved. I don't remember how, I just remember WinCE as a huge joke.

    --
    Relationship status: Available for curbside pickup.
    • (Score: 0) by Anonymous Coward on Friday August 27 2021, @09:51PM

      by Anonymous Coward on Friday August 27 2021, @09:51PM (#1171547)

      0xc0000000-0xffffffff is the top 1/4 of 32 bit memory. This range is often reserved for the OS on x86-32 so reserving it for I/O would conflict. Maybe they moved to a high-half design and blocked out 0x80000000-0xbfffffff for the OS?

    • (Score: 4, Funny) by Tork on Friday August 27 2021, @10:06PM

      by Tork (3914) on Friday August 27 2021, @10:06PM (#1171549)

      In other words, calling WinCE an RTOS was a joke.

      I respectfully disagree. I've had a few WinCE devices and I can tell you it wasn't like it was smooth sailing and then you'd hit a wall, all the wincing happened in real-time.

      --
      Slashdolt Logic: "25 year old jokes about sharks and lasers are +5, Funny." 💩
    • (Score: 2) by shortscreen on Saturday August 28 2021, @01:25AM

      by shortscreen (2252) on Saturday August 28 2021, @01:25AM (#1171596) Journal

      x86 systems (post-PCI anyway) use the latter part of the physical address space for I/O. 0xD0000000 is often used as a window to access memory on the video card. (Remember setting the AGP aperture size in the old BIOS setup?) Other PCI devices take chunks of address space up there too. That's why 32-bit Windows would top out at 3.25GB or so.

      I don't know anything about MIPS but are you sure they reserved 25% for I/O? This page says only the last 64KB http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch14s03.html [uwm.edu]

  • (Score: 0) by Anonymous Coward on Friday August 27 2021, @11:24PM (3 children)

    by Anonymous Coward on Friday August 27 2021, @11:24PM (#1171561)

    Didn't their business pretty much dried up when Apple dumped them?

    And lost more money on MIPS?

    How do they stay in business? Who funds them?

    • (Score: 2) by takyon on Saturday August 28 2021, @04:12AM

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Saturday August 28 2021, @04:12AM (#1171640) Journal

      At least that’s what the company revealed in a press release also announcing overall revenues increased by 55% to $76m in H1 2021, with $70m in cash, and no external third-party debt.

      At least some SoCs are still using their graphics. They also attempted to pivot to the automotive market. Maybe that worked.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 1, Informative) by Anonymous Coward on Saturday August 28 2021, @04:14AM (1 child)

      by Anonymous Coward on Saturday August 28 2021, @04:14AM (#1171644)

      Mips was originally SGI. And, SGI was badass back in the day. In the 90's, SGI workstations had video cards about the size of an ATX motherboard to be able to fit all the video ram on them.

      Apple didn't own nor use mips ever. At least, as a main processor.

      Apple used MOS 6502 (and Zilog z80 in an add-in card), Motorola 68000 (and lisp machine processor in an add-in card), ARM (for their newton; and they invested in ARM company), IBM PPC (with x86 in an add-in card), x86 and arm again.

  • (Score: -1, Redundant) by Anonymous Coward on Saturday August 28 2021, @08:21PM

    by Anonymous Coward on Saturday August 28 2021, @08:21PM (#1171839)

    "better known for its PowerVR embedded GPUs, Imagination Technologies"

    better known for it's disgusting slaveware GPUs, WhoreAss Technologies

    FTFY

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