The latest offering of FPGAs may have just been announced.
The ForgeFPGA devices will provide dramatic cost savings versus other alternatives, including non-FPGA designs. By providing a high level of integration, they reduce overall board and system costs. Their projected price in volume of well under US$ 0.50, opens up applications that previously couldn't use FPGAs due to cost constraints, including high-volume consumer and IoT applications.
The ForgeFPGA Family will serve applications that require less than 5,000 gates of logic, with initial device sizes of 1K and 2K Look Up Tables (LUTs). Standby power of less than 20 microamps is projected for the first devices, about half the power of competing devices. Users will be able to download the development software at no cost and with no license fees. The software offers two development modes to accommodate both new and experienced FPGA developers: a "macrocell mode" that uses a schematic capture-based development flow, and an "HDL" mode that provides a familiar Verilog environment for FPGA veterans.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @05:00PM (1 child)
Anybody experienced with the software [dialog-semiconductor.com] who'd care to comment?
(Score: 1, Interesting) by Anonymous Coward on Thursday November 18 2021, @07:03PM
These should be reverse engineered by the end of 2022, because these are about the same size as the smaller iCExx FPGAs were. At this pricepoint though, depending on the I/O tolerances and pin counts on them, these could implement a variety of 16 or very small 32 bit cpus, and depending on the pin versus cell counts, may be able to use low pin count busses at higher frequencies in over to provide 90s era i/o throughput.
(Score: 1, Funny) by Anonymous Coward on Thursday November 18 2021, @05:56PM (4 children)
Consider a beowulf-cluster of these.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @09:55PM (3 children)
and laser beam processors for all, not just the frikkin sharks of billionaires.
(Score: 2) by DECbot on Thursday November 18 2021, @11:02PM (2 children)
I'd like these with a bowl of hot grits.
cats~$ sudo chown -R us /home/base
(Score: 0) by Anonymous Coward on Friday November 19 2021, @07:38AM
No wireless. Less space than a Nomad. Lame.
(Score: 2) by maxwell demon on Friday November 19 2021, @10:21PM
In Soviet Russia, a bowl of hot grits would like these with YOU.
The Tao of math: The numbers you can count are not the real numbers.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @06:01PM (11 children)
Well, late medieval and into renaissance... when men spent a lifetime compiling logarithm tables. Now we pack basically the same into a little sliver of dedicated silicon. Then for the "end-user" the process remains much the same. For example, to multiply two numbers, look up their logs, add, look up the reverse log. Now you send it down the wire and the chip does it by way of the LuT (Look up Table).
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @06:23PM
Very cool.
(Score: 3, Informative) by shrewdsheep on Thursday November 18 2021, @06:54PM (8 children)
Multiplying two number (whether integers or floating point) is a series of shift-operations and additions. This can be very efficiently rolled out into silicon which I believe is how everybody does it. So no lookups involved.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @07:19PM (2 children)
So we are just LuT-ing the next level up from simple multiplication. Who remembers thumbing pages in a log book? Now just shift some registers, or LuT on a chip for more complex math. But the principle has not changed. Pre-computed values in a table (book or silicon).
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @08:12PM (1 child)
Ah, I'm old enough to have been taught how to use log tables in the 10th grade. (Either I'm old, or my school curriculum was horribly behind the times)
I just missed having to learn to carry a slide rule, though.
(Score: 2) by FatPhil on Friday November 19 2021, @01:25PM
A lot of the tables could have been made much more compact if people were just willing to learn summing rules. Sin(A+B) can be done to 4 significant digits just with a 90-entry table, a 100-entry table, two multiplies and an add. Of course, you're asking for mistakes to happen if you don't have electronic assistance, and if you've reached that era, it's not long until that assistance would have higher-resolution transcendental functions anyway.
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 3, Interesting) by https on Friday November 19 2021, @03:55AM (3 children)
Depends on how cheap your ROM is, for example,
http://wilsonminesco.com/16bitMathTables/index.html [wilsonminesco.com]
All computing (and algorithm) design involves tradeoffs. qsort takes a shitload more memory than swap sort. If your ram is limited you could end up looking at swap and going "Fuhhh. Gotta use it."
Offended and laughing about it.
(Score: 2) by FatPhil on Friday November 19 2021, @01:32PM (2 children)
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 2) by https on Saturday November 20 2021, @02:22AM (1 child)
Sorry, yeah, brainfart. I mean, parity error. Been a couple decades since I was debugging libraries. Merge sort?
If you're going to laugh at me, feel free to point also.
Offended and laughing about it.
(Score: 2) by FatPhil on Saturday November 20 2021, @09:37AM
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 3, Interesting) by FatPhil on Friday November 19 2021, @01:18PM
Great minds discuss ideas; average minds discuss events; small minds discuss people; the smallest discuss themselves
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @11:46PM
> ... when men spent a lifetime compiling logarithm tables. Now we pack basically the same into a little sliver of dedicated silicon
In those days it took many days to pass a message from one side of the country to another and it cost a fortune. Now I can tell you to fuck yourself instantly, for free!
(Score: 3, Interesting) by JoeMerchant on Thursday November 18 2021, @07:01PM (1 child)
I know it varies, wildly, depending on configuration, but the "ultra low power" FPGAs of 10 years back were basically space heaters. We implemented 3 NIOS cores plus a little video pipeline on one, stuff that would have drawn sub 20mW at the clock rates we were running if they were implemented in dedicated ARM cores and CMOS, instead the FPGA was drawing a couple of watts. (FPGAs with onboard high efficiency ARM cores came out just a little while after that.)
So, here you get 2K gates that draw 20uA at idle - tells me nothing, I've got a brick here that's just as useful "at idle" and it draws 0uA, what's the power consumption per FLOP - how does it compare with the ARM cores on the new RaspberryPi2W?
I don't expect FPGAs to be as efficient as dedicated CMOS, but I do expect them to report their power consumption while operating...
🌻🌻 [google.com]
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @07:39PM
Obviously hard to say what the power would be for a given design, but typically power concerns for FPGAs are dominated by static leakage power.
(Score: 3, Interesting) by anotherblackhat on Thursday November 18 2021, @07:16PM (4 children)
It's nice that I can request samples today, but what I'd really like is the datasheet.
TFA doesn't even give a part number.
Renesas is kind of infamous for a lack of supporting documentation on their parts.
(Score: 2, Interesting) by Anonymous Coward on Thursday November 18 2021, @08:20PM
Yes, without a datasheet it's not even vapor ware.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @08:47PM (1 child)
I doubt you can actually request samples today, at least not in the usual sense where they give you production parts that you can actually design into a product. You can maybe get an evaluation platforms built around test chips or perhaps even a much more expensive FPGA and probably you can only get such an item under strict NDA.
Everything about this product is currently phrased in a speculative manner such as "target standby current of 20µA", "projected price in volume of well under US$ 0.50", etc. That suggests to me like they don't actually have chips made that meet those requirements, probably because the design is not yet finished. This press release is all about generating leads.
(Score: 0) by Anonymous Coward on Friday November 19 2021, @01:07AM
(Score: 2) by driverless on Friday November 19 2021, @03:07AM
The summary is a bit inappropriate, what this is is Renesas' first entry into the FPGA market, so it's not so much a small cheap FPGA - Spartans have been around for ages - but that there's a new player in the market and that hopefully in the future that'll lead to a bit of a shakeup.
(Score: 2) by Snotnose on Thursday November 18 2021, @10:16PM (2 children)
I admit, I've only been involved in 3 use cases. 2 were multiple FPGAs on multiple boards on a PCI bus simulating a chip before going to fab. The other one was where the FPGA did the job but it wasn't cost efficient to make dedicated chips from them.
/ 1) Magis networks
// 2) Qualcomm
/// 3) I honestly can't think of the third.
When the dust settled America realized it was saved by a porn star.
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @10:55PM
(Score: 0) by Anonymous Coward on Thursday November 18 2021, @11:03PM
bus interfaces, glue logic blocks, scan converters
depending on how many I/Os they have and their characteristics
and the LUTs being talked about are M to N binary converters to replace combinatorial logic
if they have to ram, they'd be more like the original Xilinx parts, hopefully at least with
integrated bitstream eeprom