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posted by martyb on Friday December 03, @11:32AM   Printer-friendly [Skip to comment(s)]

SiFive Details New Performance P650 RISC-V Core

SiFive's Performance P650 licenseable processor IP core will debut to lead partners in Q1'2022 while the general availability is expected in "summer" 2022. Whether the Performance P650 will make its way into any public SiFive developer boards or the like remain unknown, but hopefully they will come out next year with some performant successor to the HiFive Unmatched.

This successor to their Performance P550 is expected to be the fastest RISC-V processor IP core on the market. Over the P550 should be around a 40% performance increase per-clock cycle. Overall there should be around a 50% performance gain over the P550. SiFive is reporting the Performance P650 will be faster than the Arm Cortex-A77.

SiFive Performance P650 RISC-V core to outperform Arm Cortex-A77 performance per mm2

Building upon the Performance P550 design, the SiFive Performance P650 is scalable to sixteen cores using a coherent multicore complex, and delivers a 40% performance increase per clock cycle based on SiFive engineering estimated performance in SPECInt2006/GHz, thanks to an expansion of the processor's instruction-issue width. The company compares P650 to the Arm family by saying it "maintains a significant performance-per-area advantage compared to the Arm Cortex-A77".

Other architecture enhancements over the previous generation include a higher maximum clock frequency (Liliputing says up to 3.5 GHz), platform-level memory management, interrupt control units, and support for the new RISC-V hypervisor extension for virtualization.

ARM Cortex-A77.

Previously: Intel Will License SiFive's New P550 RISC-V Core
SiFive Teases Fast New RISC-V Processor Core; Intel Acquisition Attempt Failed


Original Submission

Related Stories

Intel Will License SiFive's New P550 RISC-V Core 18 comments

Intel to make a custom SiFive-based RISC-V CPU, will be fabricated on a 7 nm node in a first step towards competing directly with Arm-based chips

The partnership will see Intel license SiFive's IP to create its own SiFive P550-based 64-bit SoC that it will fabricate on its new 7 nm node. It will form the basis of a new development platform Intel is calling Horse Creek, and will be made available to customers interested in exploring its potential in various applications involving embedded SoC tech. This could mean smartphones, but also cars, IoT products and the like. If Intel gets enough interest, it could take the relationship further. Intel hasn't yet revealed the technical specifications of the SoC, so we don't know whether it will be a single-core or multi-core platform, although the latter is likely. It's GPU tech is also unknown at this time, but Xe-based graphics are likely.

While the first Horse Creek SoCs will be ready next year, it isn't likely we will see any Intel RISC-V-based chips in commercially available products until 2023 at least.

SiFive recently announced two new high-performance 64-bit RISC-V cores, the Performance P550 and Performance P270:

SiFive compares the Performance P550 core to Arm's Cortex-A75 with higher performance in SPECint2006 and SPECfp2006 integer/floating-point benchmark, all [in] a much smaller area which would enable a quad-core P550 cluster on about the same footprint as a single Cortex-A75 core.

See also: Ubuntu 20.04/21.04 64-bit RISC-V released for QEMU, HiFive boards

Previously: Intel May Attempt to Acquire SiFive for $2 Billion


Original Submission

SiFive Teases Fast New RISC-V Processor Core; Intel Acquisition Attempt Failed 12 comments

We're closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming

SiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm.

The yet-unnamed high-performance design is within reach of Intel's Rocket Lake family, introduced in March, and Arm's Cortex-A78 design, announced last year, in terms of single-core performance, James Prior, senior director of product marketing and communications at SiFive, told The Register.

San Francisco-based SiFive didn't provide specific comparative benchmarks, so you'll have to take their word for it, if you so choose.

[...] SiFive's latest design, which is set to be teased today, will be christened with a formal name at the RISC-V Summit in December.

The CPU core is said to be about 50 per cent faster than its predecessor, the P550, which was introduced in June. We note that the L3 cache memory capacity has been quadrupled, from the 4MB in the P550 to 16MB in the new design. Up to 16 of these new cores can be clustered versus the maximum of four for the P550. The latest design can also run up to 3.5GHz compared to 2.4GHz for the P550.

Intel's Attempt to Acquire SiFive for $2 Billion Fell Apart, Report Claims

While Intel was interested to acquire RISC-V processor developer SiFive and SiFive is considering its strategic options, the companies could not agree neither on financial terms nor on how SiFive technologies could be used at Intel reports Bloomberg. The latter company is still considering both an initial public offering (IPO) as well as a takeover by a larger player.

Previously: SiFive Announces HiFive Unmatched Mini-ITX Motherboard for RISC-V PCs
Intel May Attempt to Acquire SiFive for $2 Billion
Intel Will License SiFive's New P550 RISC-V Core


Original Submission

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  • (Score: 4, Interesting) by DannyB on Friday December 03, @04:43PM (2 children)

    by DannyB (5839) Subscriber Badge on Friday December 03, @04:43PM (#1201846) Journal

    I for one welcome our new RISC-V overlords.

    I notice there is movement on porting Java to RISC-V. Porting Java to any new platform is a monumental effort. Like Linux. Java is "almost" an OS in the sheer scope of everything it covers because everything you can possibly do is portable across platforms. (Network, Filesystems, Multi Threading, Audio, MIDI, GUI, just for starters.)

    I notice IBM's Open J9 is being ported. [youtube.com] This JVM was independently developed by IBM. Open J9 is available for other OSes including Windows on Intel and Linux on Intel, and naturally IBM Mainframes.

    There also seems to be a GitHub [github.com] for porting the OpenJDK to RISC-V. The OpenJDK is upstream of what Oracle builds from.

    The major difference between OpenJDK and OpenJ9 is that OpenJDK may compile JVM bytecode to native code twice where IBM's Open J9 always compiles JVM bytecode to native code exactly once when it is first used.

    --
    Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
    • (Score: 0) by Anonymous Coward on Friday December 03, @05:30PM (1 child)

      by Anonymous Coward on Friday December 03, @05:30PM (#1201865)

      chips are build FOR java not the other way around.
      the "run-everywhere" is acctually declaring the software as solid and unmovable whilst the hardware(lol) has to move around it (for speed and efficience). it's a totally upside down paradigm....
      my "computer science history" is prolly rusty, but historically hardware was build so most nearly all possible most basic logic would work, so the "creative juices" of "logic assemblers" -aka- programmers -aka- logic artists could run wild.
      what java does is define laws and axioms and tells god to implement a universe for those.

      • (Score: 3, Funny) by DannyB on Friday December 03, @06:07PM

        by DannyB (5839) Subscriber Badge on Friday December 03, @06:07PM (#1201880) Journal

        the "run-everywhere" is acctually declaring the software as solid

        In the early days of Java it was obvious that the intended meaning of "run everywhere" was that no matter what platform you use Java on, you cannot feel safe, and must run. Alas, this original meaning was lost as Java improved over the last couple decades.

        what java does is define laws and axioms and tells god to implement a universe for those.

        Actually, I think that gets it right.

        One good example would be Java's memory model. It defines specific semantics, you can depend on, for when and not when you can reliably access a variable from multiple threads. It is very specific about when you can rely on all threads' view of memory to be coherent and in sync. You don't have to worry about how the magic works under the hood. The magicians have taken care of it. Your multiple threading code is portable and will work.

        --
        Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
  • (Score: 1, Insightful) by Anonymous Coward on Friday December 03, @05:19PM (8 children)

    by Anonymous Coward on Friday December 03, @05:19PM (#1201862)

    if it cannot run a VANILLA arch-riscV linux it's goin straight to the can, 'cause it's just a consumer hostile repeat of the ARM story... which should just be renamed "drop-the-microphone-for-profit" stand-in chip design license shill company.

    i find it always wonderful how the "consumer" is never the "invester" nowadays ...

    • (Score: 2) by DannyB on Friday December 03, @05:25PM (7 children)

      by DannyB (5839) Subscriber Badge on Friday December 03, @05:25PM (#1201863) Journal

      You might find this page interesting. port of Debian for the RISC-V architecture called riscv64 [debian.org]

      In this project the goal is to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA:

              Software-wise, this port targets the Linux kernel

              Hardware-wise, the port targets the 64-bit variant, little-endian

      This ISA variant is the "default flavour" recommended by the designers, and the one that seems to attract more interest for planned implementations that might become available in the next few years (development boards, possible consumer hardware or servers).

      While 32-bit and 128-bit implementations are possible, there are problems with this:

              In the context of RISC-V design, they have not been explored as deeply, and tools and resources (e.g. simulators, research cores) as not as well studied and adapted;

              For general purpose computers, the focus shifted to 64-bit for many years already, and there isn't a lot of interest in 32-bit architectures except for specific purposes;

              32-bit ports in Debian already struggle to compile some large packages of the archive in the last few months/years, a problem that will become worse with time;

              A 128-bit port is simply not realistic at this time.

      --
      Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
      • (Score: 0) by Anonymous Coward on Friday December 03, @05:34PM (6 children)

        by Anonymous Coward on Friday December 03, @05:34PM (#1201867)

        thank you.
        so the possible trap has been noticed ... curious if the watchtowers mand by open-source voluntaries will be enough against a well-funded (but but profits) fragmentation attack from "huge personal-data-managin-server-farms"...

        • (Score: 0) by Anonymous Coward on Friday December 03, @05:51PM (5 children)

          by Anonymous Coward on Friday December 03, @05:51PM (#1201875)

          ah, also "public" wireless networks (mobilenphone) are fantastic rich/goldmine. and these have a interest to have your communication device locked down. so a "open chip brain" that is master over the air-interface (radio that connects to their network) is also something they fear.
          i suppose a "mobile phone" without "public radio" but only wifi and a open cpu is okay, but as soon as mobile-phone-network chip needs to go in ... can you say "closed and locked down".
          the government on your behalf has sold our public collective right over certain frequences afterall (tho i am not sure if that includes spying and collecting personal information over those airwaves too?)

          • (Score: 4, Interesting) by DannyB on Friday December 03, @06:35PM (4 children)

            by DannyB (5839) Subscriber Badge on Friday December 03, @06:35PM (#1201892) Journal

            Here is how I understand the state of things. (Feel free to correct and point out any misunderstandings I have.)

            RISC-V is an ISA, not any specific hardware. Anyone can build their own chips which implement the ISA and they do not have to disclose their intellectual property about their chip implementations. Anyone can add new instructions.

            Obviously it is beneficial for software if there are common widely recognized sets of instructions that are implemented. [riscv.org] Go to this GitHub page [github.com] and click on this link (riscv-spec.pdf). On page 12 of the PDF you are in the table of contents. Notice different chapters that begin like "RV32E", "RV64I", etc. These are the names of various compatibility levels. Whether the processor is 32, 64 or 128 bit. This Wikipedia article [wikipedia.org] explains the meaning of the various instruction set extensions.

            RV32I - 32 bit, Integer add/subtract -- good for, say, a microwave oven microcontroller
            RV64I - 64 bit, Integer add/subtract
            RV128I - 128 bit, Integer add/subtract

            Additional suffixes:
            M - Integer multiplication division
            A - Atomic instruction extensions
            F - single precision floating point
            D - double precision floating point
            (. . . omitting a number of extensions here, see the Wikipedia article . . . )
            V - for vector operations
            K - for Kryptography instructions
            H - for Hypervisor instructions

            Since the extensions M, A, F and D (see list above) are so commonly necessary for most porpoises, the four extensions together MAFD can be abbreviated as G.

            So a processor that conforms to RV64G, has 64 bit word length, and Integer multiply/divide instructions, the atomic instructions, and single and double floating point instructions.

            Now extending the RV64G (which really means RV64MAFD) further, we could add C for the compact instruction format extension. This processor would be called RV64GC. The compact instruction extensions mean that some very common instructions have a more compact bit representation but do exactly the same thing. So compilers could generate the compact instructions if those compilers target any of the processors with C in their name, such as RV64GC.

            So if you go to any hardware vendor who makes chips, and they say their chip implements RV64GC, then you can count on it having all of the instructions in that specification. It could furthermore implement additional instructions, such as K for cryptography. But your compiler that targets RV64GC would still work fine on an RV64GCK chip.

            From reading on Hacker News the other day . . . there will be various "profiles", such as a "Linux profile" that is a particular set of instruction set extensions that any chip is expected to have if the chip maker expects it to run Linux. But there could be other profiles such as a supercomputer profile, or a microwave oven controller profile. The supercomputer profile might be a superset of the "linux profile".

            I hope that is helpful.

            --
            Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
            • (Score: 2, Interesting) by Anonymous Coward on Friday December 03, @07:02PM (2 children)

              by Anonymous Coward on Friday December 03, @07:02PM (#1201904)

              A Linux profile isn't the issue, it's lack of drivers and tivoization.

              Linux on ARM is an unholy mess. Google is promising to deliver a roadmap of Project Mainline at around Android 15 but for single board computers it's still hack a vendor's Linux and uboot kernel forks and hope someone at armbian has the same board. RPi is only functional because the foundation hired developers to reverse engineer a lot of proprietary Broadcom stuff such as VideoCore.

              Risc-V attempts to address some of that in a cleaner way - which is why Haiku was able to bootstrap the platform in a few months rather than the decades the ARM port has languished.

              But if the only affordable riscv board has some crappy PowerVR GPU in it, hard pass - I'll buy an off the shelf x86.

              • (Score: 3, Insightful) by DannyB on Friday December 03, @07:29PM (1 child)

                by DannyB (5839) Subscriber Badge on Friday December 03, @07:29PM (#1201908) Journal

                I remember once upon a time when the common wisdom was that Linux would always be an obscure niche product that could never gain major commercial traction.

                Now here we are. Linux has taken over the world. It is in everything around us. Even a Windows fanboi has more Linux machines than Windows machines.

                Microsoft has embraced open source. Recognized the need to build WSL.

                I have hope that RISC-V will upset the locked down chip industry. Why is ARM the only other company making an Intel compatible chip? Oh, yeah, because the architecture is closed and requires licensing.

                --
                Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
                • (Score: 2) by DannyB on Monday December 06, @03:45PM

                  by DannyB (5839) Subscriber Badge on Monday December 06, @03:45PM (#1202514) Journal

                  Sorry I meant AMD not ARM making intel compatible.

                  --
                  Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
            • (Score: 0) by Anonymous Coward on Saturday December 04, @03:50PM

              by Anonymous Coward on Saturday December 04, @03:50PM (#1202110)

              thank you for elaborate reply. my post was uninformed fear-mongering (or was it)?
              so i suppose it's arm allover again, just without the "license" burden ...
              it's not well light yet, but thru the mist and shadows it seems to be a chocolate bar with ridges and intentional fraction points ... *shrug*.
              but again, thanks for reply.
              the world can't even agree on a global "socket electricity" standard (or plug shape for that matter) so maybe it's just that x86 is acctually the real unicorn :)

  • (Score: 2) by DannyB on Friday December 03, @07:31PM (4 children)

    by DannyB (5839) Subscriber Badge on Friday December 03, @07:31PM (#1201911) Journal

    SiFive's new chip could lead to revamped phone brains in 2023 [cnet.com]

    The Performance P650, a RISC-V processor family member, is 50% faster than its predecessor but slower than top-end chips in Samsung and Apple smartphones.

    A startup called SiFive announced a new processor design Thursday that could revamp mobile phones, cars and other digital devices if the company's plans work out. Its Performance P650 design comes with a 50% speed boost over the P550 that arrived in June.

    The San Mateo, California-based company hopes its designs will offer a better balance of speed, battery life and cost thanks to a fresh start in chip engineering. The new approach comes from an effort called RISC-V that's backed by university researchers and now a lot of tech companies, too.

    Even with the significant backing, it'll be difficult to get the RISC-V family to catch on widely in an industry that prefers the broadest technology foundations. That's why chip families like MIPS, Alpha, Itanium and PA-RISC were squeezed out of the computing industry. Survivors, like the x86 chips from Intel and AMD and the Arm chips from Qualcomm, Samsung and Apple, ship by the millions each year.

    But if SiFive succeeds with its longer-term plans, you could get a SiFive-powered phone in a couple of years.

    --
    Shhhhh! Don't tell anyone . . . the microchips are not in the vaccine but are in the Ivermectin!
    • (Score: 2) by takyon on Friday December 03, @08:06PM (3 children)

      by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 03, @08:06PM (#1201938) Journal

      I think new budget phone SoCs these days still get a couple of A76 cores, so there's definitely a path for SiFive to have a better option if 8x P650 compares well to something like 2x A76 + 6x A55 in all of performance, power efficiency, and die area.

      I don't know if the cores like P650 are starting to get bloated now but SiFive made big claims about the P550, like it could fit quad-core P550 in the area of a single Cortex-A75. They should compare them to Cortex-A55 and Cortex-A510 if a RISC-V performance core can demolish it like that.

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 0) by Anonymous Coward on Friday December 03, @10:09PM (2 children)

        by Anonymous Coward on Friday December 03, @10:09PM (#1201974)

        The question for me - who is actually going to fab these SiFive designs into a handset?

        A phone is more than a CPU, you also have to license a 4G modem. I could see a niche player like Purism or Pine64 adopting this but that niche is a few thousand compared to the millions per annum the big players sell.

        Chinese researchers are eager to switch to riscv but they're more likely to use their own western-free IP and partner with a homegrown modem such as unisoc or, gasp, a reborn Huawei.

        Don't mean to FUD because I could see a riscv machine becoming my main home machine with 5 years if these SiFive ones delivered bang for buck over Celeron NUCs.

        • (Score: 2) by takyon on Friday December 03, @10:30PM (1 child)

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday December 03, @10:30PM (#1201979) Journal

          Well, I subbed this a few days ago:

          First RISC-V Smartphones Could Launch in 2022 [soylentnews.org]

          Sipeed recently tweeted a short video depicting its RISC-V RV64-powered smartphone prototype running Android 10. If all goes well, the Chinese company expects to release the first commercial models in 2022.

          [...] The flexibility and ease of development brought on by the latest iterations of the RISC-V ISA have also been noticed by Intel and Apple recently, but this architecture seems more appealing to Chinese tech producers that intend to cut ties with the Western world and reduce reliance on US-owned patents as much as possible. To this effect, Alibaba already managed to port Android 10 on RISC-V about a year ago via the T-Head XuanTie board. More recently, Sipeed tweeted a video of what looks to be an Android 10 device with a 7-inch touchscreen powered by the XuanTie C901 board.

          That product would probably be like a PinePhone: a mess. But if China gets serious about RISC-V, it will happen.

          --
          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
          • (Score: 0) by Anonymous Coward on Saturday December 04, @12:14AM

            by Anonymous Coward on Saturday December 04, @12:14AM (#1202004)

            Understood that the Chinese will make a phone sooner rather than later but that's Xuantie, not SiFive.

            Were I an investor I would not bet SiFive's farm on cell phones.

            Unless Intel has major plans for Horse Creek, I can't see any medium player such as Nokia or Moto ditching Snapdragon or Mediatek for SiFive Inside.

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