Big Trouble in Little Interconnects:
Interconnects—those sometimes nanometers-wide metal wires that link transistors into circuits on an IC—are in need of a major overhaul. And as chip fabs march toward the outer reaches of Moore's Law, interconnects are also becoming the industry's choke point.
"For some 20-25 years now, copper has been the metal of choice for interconnects. However we're reaching a point where the scaling of copper is slowing down," IBM's Chris Penny, told engineers last month at the IEEE International Electron Device Meeting (IEDM). "And there is an opportunity for alternative conductors."
Ruthenium is a leading candidate, but it's not as simple as swapping one metal for another, according to research reported at IEDM 2022. The processes of how they're formed on a chip must be turned upside down. These new interconnects will need a different shape and a higher density. These new interconnects will also need better insulation, lest signal-sapping capacitance take away all their advantage. Even where the interconnects go is set to change, and soon. But studies are starting to show, the gains from that shift come with a certain cost.
Among the replacements for copper, ruthenium has gained a following. But research is showing that the old formulas used to build copper interconnects are a disadvantage to ruthenium. Copper interconnects are built using what's called a damascene process. First chip makers use lithography to carve the shape of the interconnect into the dielectric insulation above the transistors. Then they deposit a liner and a barrier material, which prevents copper atoms from drifting out into the rest of the chip to muck things up. Copper then fills the trench. In fact, it overfills it, so the excess must be polished away.
All that extra stuff, the liner and barrier, take up space, as much as 40-50 percent of the interconnect volume, Penny told engineers at IEDM. So the conductive part of the interconnects are narrowing, especially in the ultrafine vertical connections between layers of interconnects, increasing resistance. But IBM and Samsung researchers have found a way to build tightly-spaced, low-resistance ruthenium interconnects that don't need a liner or a seed. The process is called spacer assisted litho-etch litho-etch, or SALELE, and, as the name implies, it relies on a double helping of extreme-ultraviolet lithography. Instead of filling in trenches, it etches the ruthenium interconnects out of a layer or metal and then fills in the gaps with dielectric.
The researchers achieve the best resistance using tall, thin horizontal interconnects. However, that increases capacitance, trading away the benefit. Fortunately, due to the way SALELE builds vertical connections called vias—on top of horizontal interconnects instead of beneath them—the spaces between slender ruthenium lines can easily be filled with air, which is the best insulator available. For these tall, narrow interconnects "the potential benefit of adding an air gap is huge... as much as a 30 percent line capacitance reduction," said Penny.
