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posted by janrinok on Tuesday May 09 2023, @02:14PM   Printer-friendly

Samsung to unveil first details about SF3 process technology with MBCFETs:

Although Samsung Foundry started to produce chips using its SF3E (aka 3nm gate-all-around early) manufacturing technology last June, the company only uses this tech for select chips, and it's not expected to be used widely. Meanwhile, the company is working on its second-gen 3nm-class node called SF3 (3GAP) and will disclose more information about it at the upcoming 2023 Symposium on VLSI Technology and Circuits in Kyoto, Japan.

Samsung's Sf3 (3nm-class) fabrication technology (set to be introduced at the T1-2 session) will use the company's second-gen Multi-Bridge-Channel field-effect transistors (MBCFET). This new fabrication technology builds upon the first-gen GAA device (SF3E) that's already in mass production, incorporating further optimization.

Samsung claims that compared to SF4 (4LPP, 4nm-class, low power plus), SF3 offers a 22% higher performance at the same power and transistor count, a 34% power reduction at the same clocks and complexity, and a 0.79x logic area reduction. However, Samsung doesn't compare its SF3 to SF3E, and there is no word about the SRAM and analog circuit scaling.

One of the main benefits of GAA transistors over FinFET devices is the reduced leakage current since their gate is surrounded by the channel on all four sides. Additionally, the channel thickness can be adjusted to enhance performance or reduce power consumption.

Samsung now says that the SF3 platform offers greater design flexibility enabled by various nanosheet (NS) widths of the MBCFET device within the same cell type. It is unclear whether it means that the original SF3E lacks one of the key capabilities of GAA transistors, but Samsung's phrasing at least implies it.

An image that Samsung demonstrates in its paper depicts damage on top of the nanosheet during the metal gate process, so we may speculate that one of the aspects that the company will cover are production challenges it encountered with its GAA-based SF3E production node.

Interestingly, recently the company admitted that its fabrication processes are behind those of TSMC, and it will take at least five years to catch up.


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  • (Score: 2) by takyon on Tuesday May 09 2023, @03:17PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday May 09 2023, @03:17PM (#1305531) Journal

    there is no word about the SRAM and analog circuit scaling.

    Scaling will be bad like everyone else's, but designers can cut the amount of SRAM per core and get away with it (e.g. Zen 4c) or better yet, put in 3D SRAM.

    We can already get 8 CPU cores in almost everything using very little silicon. Efficiency gains are the most important thing these days.

    TSMC is going for GAAFETs at N2, with similar improvements. Maybe better density since they report the "mixed" number, and Samsung's 0.79x for logic scaling isn't that great.

    https://www.anandtech.com/show/18832/tsmc-outlines-2nm-plans-n2p-brings-backside-power-delivery-in-2026-n2x-added-to-roadmap [anandtech.com]

    When introducing this technology last year, TSMC said that it would enhance transistor performance by 10% to 15% with the same power and complexity, or reduce power consumption by 25% to 30% at the same clock and transistor count. The company also says that N2 will offer 'mixed' chip densities of over 15% greater than N3E, which is an increase from the 10% density increase announced last year.

    Backside power delivery is another thing to watch out for, maybe a half node improvement from that alone:


    Backside power delivery is meant to decouple I/O and power wiring by moving power rails to the back, addressing challenges like elevated via resistances in the back-end-of-line (BEOL). This, in turn, will enhance transistor performance and reduce their power consumption. Also, backside power deliver eliminates some potential interference between data and power connections.

    Backside power delivery is innovation whose importance is hard to overstate. Chipmakers have been fighting resistances in chip power delivery circuitry for years, and backside power delivery networks (PDN) are a yet another method to address them. In addition, decoupling PDN and data connections also helps with area reduction, so expect N2P to further increase transistor density compared to N2.

    For now, TSMC is not disclosing any hard numbers regarding N2P's performance, power, and area (PPA) advantages over N2. But based on what we hear from industry sources, backside power rails alone could bring a single digit power improvements and double-digit transistor density improvements.

    TSMC says that N2P is on track to be production ready in 2026, so we can speculate that the first N2P-based chips will be available in 2027. This timeline would put TSMC roughly two years behind rival Intel when it comes to backside power, assuming they're able to ship their own 20A process on time in 2024.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
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