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posted by janrinok on Monday May 22 2023, @05:31PM   Printer-friendly

https://www.devever.net/~hl/regmap

If you've ever had to write a program which interfaces directly with hardware — perhaps while writing a program for an MCU or embedded system or a kernel driver — you may have noticed a few common patterns in register map behaviour and design. I'm not sure anyone has ever really collected them together, so I decided to make a list of all the ones I can think of.


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  • (Score: 2) by maxwell demon on Monday May 22 2023, @06:14PM

    by maxwell demon (1608) on Monday May 22 2023, @06:14PM (#1307408) Journal

    The 8m register is names as if its width were an integerpower of 8. But half of the sizes aren't. Only 8 = 81 and 64 = 82 are.

    --
    The Tao of math: The numbers you can count are not the real numbers.
  • (Score: 4, Informative) by VLM on Monday May 22 2023, @06:22PM (1 child)

    by VLM (445) on Monday May 22 2023, @06:22PM (#1307409)

    Some old timer stuff you don't see much after 1980 or so...

    autoincrement indirect access registers like the pdp-8. If you're always going to inc after an indirect read, heck, make it automatic. The pdp-8 had 8.

    The registers connected to each other. 6809 has 8 bit reg A and B connected to D. In a sense, rotate and shift can be done with registers connected to each other. Some architectures had the carry register as a literal register not a condition code register.

    The article mentions "special" registers to do status/wait/done but there are more extreme examples where ALU register r0 is not just some random ALU register, its also the program counter. Almost as "interesting" as designs where the PC is also memory location 0x0000 or similar. Also along the lines of "special" register see various large memory schemes looking like segment registers or fancier MMU registers.

    • (Score: 5, Informative) by stormreaver on Monday May 22 2023, @09:29PM

      by stormreaver (5101) on Monday May 22 2023, @09:29PM (#1307466)

      6809 has 8 bit reg A and B connected to D.

      A more elegant CPU for a more civilized age. I had a CoCo 3 (which had the 6809) and an IBM Compatible (remember those?) with an 8088. The 6809 ran rings around the 8088, and did so at a small fraction of the CPU speed. The 6809 was a pleasure to program, and the 8088 was close to nightmarish by comparison. There were many times when programming the 8088 that I said out loud, "That's idiotic!" about the Intel instruction set.

  • (Score: 2) by turgid on Monday May 22 2023, @08:44PM (7 children)

    by turgid (4318) Subscriber Badge on Monday May 22 2023, @08:44PM (#1307454) Journal

    The first time I came across this I was stunned. Why did hardware need a /dev/null?

    No, that's not what it was for.

    Still, it's one of those mysteries how it works or why you wouldn't be able to (or want to) read it back. It's a trivial software change to "remember" the last value written if you really need to (to make the rest of the program simpler).

    • (Score: 3, Funny) by RS3 on Monday May 22 2023, @09:36PM

      by RS3 (6367) on Monday May 22 2023, @09:36PM (#1307469)

      The write-only register is used in address dereferencing calculations when working with write only memory [repeater-builder.com].

      (for those who might not have grasped it, this is a joke).

    • (Score: 3, Interesting) by KilroySmith on Monday May 22 2023, @10:07PM

      by KilroySmith (2113) on Monday May 22 2023, @10:07PM (#1307481)

      I had to fight the battle over write only registers with our chip designers one time. This was in the age when transistors on a a die were expensive; adding in the read circuitry for all the registers on chip made the die noticeably larger, thus noticeably more expensive. I haven’t seen such a thing in ages, because transistors are now remarkably cheap and that battle never needs to be fought.

    • (Score: 5, Informative) by owl on Monday May 22 2023, @10:25PM (2 children)

      by owl (15206) on Monday May 22 2023, @10:25PM (#1307487)

      The first time I came across this I was stunned. Why did hardware need a /dev/null?

      Nor did I, when I first encountered it on the Dec Alpha CPU. One of it's registers was wired up to always read zero, and always consume and throw away a write without complaint (effectively a /dev/null register).

      Then I dug in more, and its usefulness was in synthesizing additional addressing modes from the small set of hardware address modes the chip actually provided.

      I.e., (and this is largely from memory, so I may be off a bit) the Alpha architecture did not provide a native "load 64-bit word from address X stored in register Rx". Instead it provided a "load word from address stored in Rx indexed by offset stored in Ry" as a native mode. The "load from literal address" mode was synthesized by using R0 (assuming R0 was the "read as zero, consume all writes" register) as Ry in the addressing mod.

      So when you wrote: load R5,[R16]

      to load R5 from the address in R16, the actual CPU instruction executed was: load R5, [R16+R0]

      With R0 providing a "zero", which makes the offset addition a null operation, resulting in a load from address in R16.

      In the end, the Alpha had something like only 4 or 8 actual hardware addressing modes, but with creative use of the "zero register" the programmers had something like 16 or 24 different possible "addressing modes" that they could actually use.

      • (Score: 5, Informative) by sjames on Monday May 22 2023, @11:15PM (1 child)

        by sjames (2882) on Monday May 22 2023, @11:15PM (#1307502) Journal

        In addition, a zero register is a good way to initialize an accumulator without having an extra instruction. Writing to the zero register is a cheap to implement NOP. Add that to the inexpensive addressing flexibility and you get a lot of bang for the buck from the zero register.

        • (Score: 5, Informative) by owl on Tuesday May 23 2023, @02:17AM

          by owl (15206) on Tuesday May 23 2023, @02:17AM (#1307527)

          Now that you mention it, I think the Alpha's "nop" instruction was actually something like

          add r0,r0,r0

          (assuming r0 was the "always zero" register), that would add zero to zero and store the answer in the register that was always zero. The result, a "NOP" instruction, without having to explicitly have an actual "NOP" instruction built into the hardware.

    • (Score: 2) by sjames on Monday May 22 2023, @11:01PM

      by sjames (2882) on Monday May 22 2023, @11:01PM (#1307496) Journal

      Sometimes there is no memory behind the register. The address decode and the r/W line together through an AND gate triggert some action. There is nothing to read back.

    • (Score: 2) by Mojibake Tengu on Monday May 22 2023, @11:05PM

      by Mojibake Tengu (8598) on Monday May 22 2023, @11:05PM (#1307500) Journal

      Write-only registers are usually used for controlling such hardware state, where reading back does not have any sense because the state itself is rather ephemeral in time domain (because it serializes, or just strobes some other data).
      Some examples are tape or floppy interfaces, or full duplex modem control.

      Today, it's still usual as GPIO set in OUT mode.
      Another fine example is power-off control. You don't want to read power control to determine the machine is powered off, don't you?

      --
      Rust programming language offends both my Intelligence and my Spirit.
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