Mysterious "Gator Rande" and "Medusa BB" CPUs mentioned in roadmap:
Something to look forward to: A leaked roadmap from Spanish laptop maker Seleno offers a glimpse into how Intel and AMD aim to shape the mobile CPU market through 2027. While details this far out are subject to change, the documents hint at major shifts in performance tiers, manufacturing nodes, and architecture rollouts that could influence everything from everyday laptops to next-gen gaming consoles.
Prominent leakers @x86deadandback and @momomo_us recently shared internal roadmaps from laptop manufacturer Seleno that chart mobile CPUs from Intel and AMD through 2027.
The forecast provides rough release windows for upcoming architectures, such as Panther Lake, Wildcat Lake, Medusa Point, and the successor to Fire Range. However, even if the roadmap proves accurate, details about processors scheduled to launch two years from now are likely subject to change.
The laptop maker expects to release laptops featuring 12-core Gorgon Point CPUs throughout 2026. This 4nm, Zen 5-based lineup will succeed Strix Point and Kraken Point in the 15 – 54W upper-midrange performance tier. Seleno's chart, however, does not include performance details aside from AI TOPS.
Meanwhile, high-end devices exceeding 45W will continue using 16-core Fire Range processors through the end of 2026, while Strix Halo APUs will remain in use through 2027. Seleno plans to shift its Hawk Point laptops, which feature eight Zen 4 cores, down one performance tier next year. At the entry level, 6 – 15W products will stick with the mature Zen 2-based Mendocino processors for the foreseeable future.
Zen 6 is set to debut in 2027, with Gator Rande succeeding Fire Range and Medusa Point replacing Gorgon Point. Little is known about Gator Rande, but the roadmap supports prior leaks suggesting that Medusa Point will utilize 3nm semiconductors and the FP10 socket. Seleno also intends to replace Hawk Point with a mysterious "Medusa BB" architecture sometime in mid-2027.
APUs with Zen 6 cores and RDNA 5 (also referred to as UDNA) graphics chips are expected to power the PlayStation 6 and Microsoft's next-generation console. Meanwhile, high-end socketed Zen 6 desktop CPUs will reportedly feature more cores than Zen 5 and may reach clock speeds between 6.4 and 7 GHz.
On the Intel side, Seleno's projections only extend through 2026 and lack details on core counts or semiconductor processes. Unsurprisingly, the company plans to adopt the Panther Lake-H lineup as soon as it launches in late 2025.
Panther Lake will be built on the 18A node, which may represent Intel's last chance to regain competitiveness in the semiconductor manufacturing market.
In the 28W midrange and 15W mainstream sectors, Wildcat Lake will succeed Raptor Lake sometime next year. Although details on Wildcat Lake are scarce, Seleno's roadmap contradicts earlier speculation that it would replace Twin Lake. Instead, Twin Lake will continue powering entry-level 7 – 15W N-series laptops through mid-2026. The chart makes no mention of Nova or Bartlett Lake.
(Score: 3, Interesting) by bzipitidoo on Tuesday September 02 2025, @05:08AM (3 children)
When is x86 going away? It's a terrible architecture, crufty, lacking in registers, and still not fully virtualizable. I understand the big reason for keeping it is so that all these old binaries will still work. But that argument seems ever weaker as the years go by. First, you already have to do emulation to run a 1980s x86 binary, as it is very likely programmed to work with the long gone DOS environment, use real mode, and use the graphics, floppy drives, Soundblaster sound card, and other hardware of that era. It doesn't help that much that a DOS emulator such as DOSBox or DOSemu gets to use a lot of native instructions just because it's running on an x86. The environment most certainly can be and is emulated on non x86 architectures. Which brings me to the second point, which is that more and more, software is more open source and more portable. It's getting easier and easier to build a complete OS with thousands of utilities and apps on any architecture that has decent support for multitasking and virtualization. So what does that leave as a reason to keep all this backwards compatibility?
Is Intel capable of making a decent chip with the RISC V instruction set architecture? Why don't they? Or is it a matter of exploiting whatever patents they have on the x86 that are still in force?
(Score: 1, Informative) by Anonymous Coward on Tuesday September 02 2025, @03:41PM
and there is the problem
X86 sucks but it is a platform that a couple of billion dollar corporations drive forward
RISCV was deployed because companies like Western Digital didn't want to pay ARM license fees
Every chip vendor is coming up with incompatible extensions to the architecture to bury in their
NDA crippled SOCs
(Score: 2) by Rich on Wednesday September 03 2025, @12:49PM (1 child)
The die area of x86 that's used for preprocessing the instructions is negligible these days, and x86 still has the densest instruction set of them all. The major downside of decoding that is that you'd have a few extra pipeline stages, but again, the condition predictors have become so good that this doesn't matter either.
I guess ARM is mostly where they are now, because they offer easy turnkey solutions for anyone wanting a CPU tailored to their needs, their design scales down to "primitive" yet does not preclude a high-end solution, and last but not least, they were the first to do so.
If you'd want go get anywhere near where x86 or ARM are now, you'd need a RISC-V design that goes way beyond how these CPUs are built today. The intentional omission of conditions in their ISA leads to lower IPC than the competition. In my understanding, this has advantages for simplifying mid-range designs (e.g. the typical DLX/MIPS-heritage 5-stage pipeline they use for teaching), which should result in higher clocks, or more cores, but this hasn't materialized so far. All designs you see are worse performers than their ARM peers which not only have conditions, but conditional instructions as well. To get around this, they suggest "instruction fusing", which requires a decoder frontend that you suggested we should get away from. And even with fusing, it's a cache pig in that place. I don't really have an idea about CPU design, but if I had to deal with that issue, I would either use 34 or 36 bit registers with "invisible" result codes attached, or at least provide ALU instructions that generate the required conditions (rather than the weird code contraptions they suggest), execute in 1 extra cycle at worst, or can be fused from no more than two instructions.
(Score: 0) by Anonymous Coward on Thursday September 04 2025, @01:00AM
If I were a CPU designer nowadays, with a budget of billions of transistors. I'd work more with the smartest people in the software bunch to figure out what features might be "game-changing" useful.
For example, it should be embarrassing for the CPU designers that they only introduced stuff like the shadow stack/CET so late in the game[1]. Such ideas have been around for a long long time, that even I was wondering why there wasn't such a feature. The billion transistor budgets had been around for so many years that the CPU bunch ran out of ideas and mostly started adding more and more cores.
So maybe there could be other stuff that could improve things greatly:
https://cwe.mitre.org/top25/archive/2024/2024_kev_list.html [mitre.org]
https://en.wikipedia.org/wiki/Associative_array [wikipedia.org]
https://nima101.github.io/io_multiplexing [github.io]
https://en.wikipedia.org/wiki/C10k_problem [wikipedia.org]
https://en.wikipedia.org/wiki/Vector_Packet_Processing [wikipedia.org]
etc etc
[1] https://web.archive.org/web/20170814120442/https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf [archive.org]
https://en.wikipedia.org/wiki/Shadow_stack [wikipedia.org]
https://en.wikipedia.org/wiki/Transistor_count [wikipedia.org]