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posted by martyb on Wednesday January 20 2016, @05:52PM   Printer-friendly
from the how-much-does-it-cost? dept.

Samsung has announced the mass production of dynamic random access memory (DRAM) packages using the second generation High Bandwidth Memory (HBM2) interface.

AMD was the first and only company to introduce products using HBM1. AMD's Radeon R9 Fury X GPUs featured 4 gigabytes of HBM1 using four 1 GB packages. Both AMD and Nvidia will introduce GPUs equipped with HBM2 memory this year. Samsung's first HBM2 packages will contain 4 GB of memory each, and the press release states that Samsung intends to manufacture 8 GB HBM2 packages within the year. GPUs could include 8 GB of HBM2 using half of the die space used by AMD's Fury X, or just one-quarter of the die space if 8 GB HBM2 packages are used next year. Correction: HBM2 packages may be slightly physically larger than HBM1 packages. For example, SK Hynix will produce a 7.75 mm × 11.87 mm (91.99 mm2) HBM2 package, compared to 5.48 mm × 7.29 mm (39.94 mm2) HBM1 packages.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains over 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Samsung's new DRAM package features 256GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung's 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

TSV refers to through-silicon via, a vertical electrical connection used to build 3D chip packages such as High Bandwidth Memory.

Update: HBM2 has been formalized in JEDEC's JESD235A standard, and Anandtech has an article with additional technical details.

Previously:
AMD Teases x86 Improvements, High Bandwidth Memory GPUs
AMD Shares More Details on High Bandwidth Memory
Samsung Mass Produces 128 GB DDR4 Server Memory


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  • (Score: 3, Interesting) by jasassin on Wednesday January 20 2016, @09:11PM

    by jasassin (3566) <jasassin@gmail.com> on Wednesday January 20 2016, @09:11PM (#292249) Homepage Journal

    What does this mean? Where is the bottleneck now?

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  • (Score: 2, Insightful) by RamiK on Wednesday January 20 2016, @09:25PM

    by RamiK (1813) on Wednesday January 20 2016, @09:25PM (#292259)

    Same as it ever was forever: The stupid meatbag clicking mechanical buttons for output and reading input at a few bauds at most per char.

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  • (Score: 4, Informative) by takyon on Thursday January 21 2016, @12:52AM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday January 21 2016, @12:52AM (#292340) Journal

    On the GPU front, if we assume AMD and Nvidia uses a minimum of 8 GB of HBM2 going forward, there shouldn't really be a VRAM bottleneck for most users (parallel computing users maybe, after all, Nvidia Titan X comes with 12 GB of VRAM).

    GPUs with HBM instead of GDDR5 can have a lower TDP, or use more power elsewhere, the opposite of a bottleneck.

    AMD's APUs (combining CPU with integrated GPU) are apparently bottlenecked by memory bandwidth, and AMD plans to add HBM to some future APUs. That will increase their cost but graphics performance should go up.

    http://www.eurogamer.net/articles/digitalfoundry-2015-amd-reveals-hbm-future-of-graphics-ram-tech [eurogamer.net]
    http://www.anandtech.com/show/9390/the-amd-radeon-r9-fury-x-review/6 [anandtech.com]

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