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Tom's Hardware is reporting on Soft Machines, a startup that is creating a new CPU architecture to be used in custom processors and SoCs for partnered companies:
Soft Machines, a well-funded startup ($175 million to date) that came out of stealth last year, announced its "Virtual Instruction Set Computing" (VISC) architecture, which promises 2-4x higher performance/Watt compared to existing CPU designs.
Current CPU architectures scale performance by using wider architectures and out-of-order execution to improve instruction-level parallelism (ILP) and by adding additional cores to improve thread-level parallelism (TLP). These techniques are limited by Amdahl's law, however, leading to larger, more power-hungry processors. The challenges of multi-threaded programming, which is necessary to extract the full benefit of multiple CPU cores, also places limits on achieving high levels of TLP.
In order to improve performance/Watt scaling, Soft Machines is taking a different approach. Its architecture uses "virtual cores" (VC) that shift the burden of thread scheduling and synchronization from the software programmer and operating system to the hardware itself. With VISC, a single thread is not restricted to a single core like traditional multiprocessor designs. Instead, it gets broken down into smaller threadlets by the VCs and executes on multiple underlying physical cores (PC). By using the available execution units more efficiently, the VISC architecture, in theory, can maintain high performance even when using smaller, simpler physical cores, which reduces power consumption. Another advantage of this technique is that single-threaded applications can execute on multiple physical cores.
Soft Machines claimed that its virtual cores can either increase the performance/Watt by 2-4x at the same power consumption level, or they can decrease the power consumption by 4x at the same performance level relative to existing designs. Unlike ARM, which licenses its core design IP, or Intel, which manufactures its own cores and SoCs, Soft Machines will partner with other companies to create custom processors and SoCs.
(Score: 2) by RamiK on Monday February 08 2016, @01:10AM
The key novelty in our work is that our instruction set exposes a very small number of models of parallelism and a few memory abstractions essential for high performance algorithm development and tuning. Together, we expect that these abstractions will effectively capture a wide range of heterogeneous hardware, which would greatly simplify major programming challenges such as algorithm design, source level portability, and performance tuning.
http://rsim.cs.illinois.edu/Pubs/12-HotPar-VAdve.pdf [illinois.edu]
They designed a a low level virtual instruction set(http://llvm.org/pubs/2003-10-01-LLVA.pdf) and hardware that allocates silicone as needed rather than spiting it into predetermined fixed sizes per core. So, an Intel Core would split the silicone into two\quad\whatever equal parts. That means that some threads will idle and waste silicone while others won't have enough.
ARM went about this problem with big.LITTLE. They split their cores for the different usages they profiled off phones and servers. It's better than Intel since even servers have lots of small processes that can be shuffled around but it's still quite wasteful.
With VISC, the problem is solved when you have an optimized, ahead-of-time, runtime. A demanding single thread will get more silicone while a low demand single thread will get less. So, more silicone both per watt and per dollar. From what I can tell they already have production ready Java and LLVM backend optimizations so Android is good to go.
Read:
http://llvm.org/pubs/2003-10-01-LLVA.pdf [llvm.org]
http://rsim.cs.illinois.edu/Pubs/12-HotPar-VAdve.pdf [illinois.edu]
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