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posted by cmn32480 on Tuesday April 05 2016, @06:06PM   Printer-friendly
from the everything-is-getting-smaller dept.

Samsung Electronics has announced the production of "10nm-class" 8 gigabit DRAM chips that will be used in DDR4 modules with capacities ranging from 4 GB to 128 GB. "10nm-class" is an industry term that refers to an unspecified process somewhere between 10 nanometers and 19 nanometers.

In November, Samsung announced the production of 128 GB DDR4 registered dual inline memory modules (RDIMMs) using through silicon via (TSV) stacked dies with four 8 gigabit chips per package. Those modules used 20nm process DRAM and achieved a 2,400 Mbps data rate. The new 10nm-class memory will support a 3,200 Mbps data rate.

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  • (Score: 1, Interesting) by Anonymous Coward on Tuesday April 05 2016, @06:20PM

    by Anonymous Coward on Tuesday April 05 2016, @06:20PM (#327739)

    For the RAM:
    Is this new memory susceptible to rowhammer style attacks?
    Is it available in cost effective unregistered ECC modules?

    For the flash:
    How many write erase cycles is it good for?
    What is the MTBF?
    What is its power off data retention period? Still 10 years? Less?
    Are there any rowhamemr style leakage issues in the flash chips that could corrupt data?

    The smaller these processes get, the more concerned I am about the overall stability of the technology. It's not like these guys are trying for the best quality given the rapid turnover to be competitive on the time to market front.

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  • (Score: 3, Informative) by takyon on Tuesday April 05 2016, @06:36PM

    by takyon (881) <> on Tuesday April 05 2016, @06:36PM (#327743) Journal

    Here is a large version of the photo accompanying the press release: []

    Here are the specs of the 128 GB TSV 20nm DDR4, which is registered: []

    The website makes it fairly easy to search for other DRAM products.

    The press release mentions "4GB for notebook PCs to 128GB for enterprise servers".

    No NAND mentioned in this story.

    [SIG] 10/28/2017: Soylent Upgrade v14 []
    • (Score: 2) by Alfred on Tuesday April 05 2016, @08:06PM

      by Alfred (4006) on Tuesday April 05 2016, @08:06PM (#327770) Journal
      Whoa, check that picture. The bottom edge with the contacts is not straight. I suppose this is to keep you from seating them in a DDR3 slot but really, couldn't they just make them a different size or another notch location? I'd prefer smaller size since I like building with ITX boards.

      And how many Bubba's IT Trailers will try and shave the PCB straight to use it somewhere they shouldn't ;-)
  • (Score: 3, Insightful) by bitstream on Tuesday April 05 2016, @09:23PM

    by bitstream (6144) on Tuesday April 05 2016, @09:23PM (#327790) Journal

    My thoughts too..
    Btw, why is unregistred RAM that important? extra buffers actually increase the electrical stability.

    The path to smaller and smaller geometry will end up where the uncertainty of matter will wreck the stability of the module. The superficially solid and stable surroundings is just an illusion. In reality all matter above 0 K is shaking and there's subatomic particles shoot out at near speed of light etc. These phenoma will matter a lot less of large geometries and small number of bits. ECC or RAM-RAID will become a necessity, just like harddiscs uses advanced trellis encoding to keep bits correct and ZFS software checks them again.

    Anyone placing these memory modules near a thick concrete wall, rocks or radon site will perhaps get a free geiger counter rather than RAM. Or the chassis and 19" rack is made of Chinese steel from scrapped nuclear sites.

    And don't forget the CAS latency (CL) that will make requesting data in a random rather than a sequential order really, really slow. Notice how the "old" DDR3 interface is actually better on this.

    Any comments?