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posted by martyb on Thursday June 02 2016, @12:19PM   Printer-friendly
from the chipping-away-at-the-market dept.

A lot of CPU news is coming out of Computex 2016.

Intel has launched its new Broadwell-E "Extreme Edition" CPUs for "enthusiasts". The top-of-the-line model, the i7-6950X, now includes 10 cores instead of 8, but the price has increased massively to around $1,723. Compare this to a ~$999 launch price for the 8-core i7-5960X or 6-core i7-4960X flagships from previous generations.

Intel has also launched some new Skylake-based Xeons with "Iris Pro" graphics.

AMD revealed more details about the Radeon RX 480, a 14nm "Polaris" GPU that will be priced at $199 and released on June 29th. AMD intends to compete for the budget/mainstream gamer segment falling far short of the $379 launch price of a GTX 1070, while delivering around 70-75% of the performance. It also claims that the RX 480 will perform well enough to allow more gamers to use premium virtual reality headsets like the Oculus Rift or HTC Vive.

While 14nm AMD "Zen" desktop chips should be coming later this year, laptop/2-in-1/tablet users will have to settle for the 7th generation Bristol Ridge and Stoney Ridge APUs. They are still 28nm "Excavator" based chips with "modules" instead of cores.

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  • (Score: 2) by opinionated_science on Friday June 03 2016, @03:49PM

    by opinionated_science (4031) on Friday June 03 2016, @03:49PM (#354600)

    that's what I was referring too - but originally (and I dug around the APU I had to hand A10 something) the GPU was on the otherside of a PCI bus, inside the CPU package!!

    If I understand correctly Hypertransport is more efficient (allows interleaved transfer) but is only used for CPU-CPU and CPU-MEM.

    For GPU's to work, they use PCI as they can be directly addressed from the CPU via PCI, as well as be a DMA master.

    If new architectures share GPU/CPU memory with lower latency (1 us), I would be very interested.

    As of now, plans are to load as much on the GPU and let it rip - hence my number 12 Tflops. I calculated it a few years ago, though someone actually built a machine that solves the problem out of custom ASICs...

      (Google Anton, D.E. Shaw)

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