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posted by mrpg on Wednesday March 08 2017, @04:03AM   Printer-friendly
from the we-needed-one-in-december dept.

Ryzen was an important launch for AMD. Arguably more important? Its rollout of x86 "Naples" server chips:

For users keeping track of AMD's rollout of its new Zen microarchitecture, stage one was the launch of Ryzen, its new desktop-oriented product line last week. Stage three is the APU launch, focusing mainly on mobile parts. In the middle is stage two, Naples, and arguably the meatier element to AMD's Zen story. A lot of fuss has been made about Ryzen and Zen, with AMD's re-launch back into high-performance x86. If you go by column inches, the consumer-focused Ryzen platform is the one most talked about and many would argue, the most important. In our interview with Dr. Lisa Su, CEO of AMD, the launch of Ryzen was a big hurdle in that journey. However, in the next sentence, Dr. Su lists Naples as another big hurdle, and if you decide to spend some time with one of the regular technology industry analysts, they will tell you that Naples is where AMD's biggest chunk of the pie is. Enterprise is where the money is.

[...] The top end Naples processor will have a total of 32 cores, with simultaneous multi-threading (SMT), to give a total of 64 threads. This will be paired with eight channels of DDR4 memory, up to two DIMMs per channel for a total of 16 DIMMs, and altogether a single CPU will support 128 PCIe 3.0 lanes. Naples also qualifies as a system-on-a-chip (SoC), with a measure of internal IO for storage, USB and other things, and thus may be offered without a chipset. Naples will be offered as either a single processor platform (1P), or a dual processor platform (2P). In dual processor mode, and thus a system with 64 cores and 128 threads, each processor will use 64 of its PCIe lanes as a communication bus between the processors as part of AMD's Infinity Fabric. The Infinity Fabric uses a custom protocol over these lanes, but bandwidth is designed to be on the order of PCIe. As each core uses 64 PCIe lanes to talk to the other, this allows each of the CPUs to give 64 lanes to the rest of the system, totaling 128 PCIe 3.0 again.

[...] While not specifically mentioned in the announcement today, we do know that Naples is not a single monolithic die on the order of 500mm2 or up. Naples uses four of AMD's Zeppelin dies (the Ryzen dies) in a single package. With each Zeppelin die coming in at 195.2mm2, if it were a monolithic die, that means a total of 780mm2 of silicon, and around 19.2 billion transistors – which is far bigger than anything Global Foundries has ever produced, let alone tried at 14nm. During our interview with Dr. Su, we postulated that multi-die packages would be the way forward on future process nodes given the difficulty of creating these large imposing dies, and the response from Dr. Su indicated that this was a prominent direction to go in.

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  • (Score: 0) by Anonymous Coward on Wednesday March 08 2017, @04:07AM (3 children)

    by Anonymous Coward on Wednesday March 08 2017, @04:07AM (#476315)

    I haven't seen it specifically referenced...

  • (Score: 1, Informative) by Anonymous Coward on Wednesday March 08 2017, @04:21AM

    by Anonymous Coward on Wednesday March 08 2017, @04:21AM (#476320)

    Ryzen (the desktop version out now) supports ECC RAM, so I assume the server version will as well.

    Source: []

  • (Score: 2) by TheReaperD on Wednesday March 08 2017, @04:26AM (1 child)

    by TheReaperD (5556) on Wednesday March 08 2017, @04:26AM (#476322)

    Though I haven't seen it specifically referenced, I cannot see a business class architecture coming out without ECC support. It would be a non-starter.

    Ad eundum quo nemo ante iit
    • (Score: 2, Informative) by Anonymous Coward on Wednesday March 08 2017, @05:31AM

      by Anonymous Coward on Wednesday March 08 2017, @05:31AM (#476341)

      Yes the chips have ECC support. No the software support is likely not there yet for the desktop.

      It should be by the time the server chips are out, and this and discovering teething problems before the Q2 release are likely why the consumer chips were released now. Get the early adopter enthusiasts to field your 'beta' chips, then have the errata solved in time for the enterprise RTM chip revisions.