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posted by CoolHand on Thursday March 30 2017, @07:07PM   Printer-friendly
from the we-want-moore dept.

Intel is talking about improvements it has made to transistor scaling for the 10nm process node, and claims that its version of 10nm will increase transistor density by 2.7x rather than doubling it.

On the face of it, three years between process shrinks, rather than the traditional two years, would appear to end Moore's Law. But Intel claims that's not so. The company says that the 14nm and 10nm process shrinks in particular more than doubled the transistor density. At 10nm, for example, the company names a couple of techniques that are enabling this "hyperscaling." Each logic cell (an arrangement of transistors to form a specific logic gate, such as a NAND gate or a flip flop) is surrounded by dummy gates: spacers to isolate one cell from its neighbor. Traditionally, two dummy gates have been used at the boundary of each cell; at 10nm, Intel is reducing this to a single dummy gate, thereby reducing the space occupied by each cell and allowing them to be packed more tightly.

Each gate has a number of contacts used to join them to the metal layers of the chip. Traditionally, the contact was offset from the gate. At 10nm, Intel is stacking the contacts on top of the gates, which it calls "contact over active gate." Again, this reduces the space each gate takes, increasing the transistor density.

Intel proposes a new metric for measuring transistor density:

Intel wants to describe processes in terms of millions of logic transistors per square millimeter, calculated using a 3:2 mix of NAND cells and scan flip flop cells. Using this metric, the company's 22nm process managed 15.3 megatransistors per millimeter squared (MTr/mm2). The current 14nm process is 37.5MTr/mm2, and at 10nm, the company will hit 100.8MTr/mm2. Competing 14nm/16nm processes only offer around 28MTr/mm2, and Intel estimates that competing 10nm processes will come in at around 50MTr/mm2.

See also: the International Roadmap for Devices and Systems.

A number of stories here have covered the advancement to 10nm chips: Samsung: Exynos, TSMC: MediaTech Helio X30 for example. A reoccuring comment in the discussions is if 10nm from Samsung is equivalent to 10nm for TSMC or Intel.

Intel's Mark Bohr discussed the difficulty of comparing process nodes during Manufacturing Day, specifically proposing to move the industry to transistor density as a comparative metric. Surprisingly enough, Intel claims their 10nm process is roughly twice as dense of the competition. Intel is not the only ones frustrated by comparing process nodes, as this recent article tries to compare current "14nm" nodes between the major vendors.

To further confuse the discussion is new 22nm processes: Global Foundries 22nm FD-SOI and Intel's just announced 22FFL process, both targeting energy efficient devices. GF's is in high volume manufacturing already while Intel's is just announced, but further cement's Intel's delve into foundry work.

These topics are largely covered by EETimes' summary of Intel's recent announcements

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  • (Score: 3, Informative) by takyon on Thursday March 30 2017, @07:49PM (3 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday March 30 2017, @07:49PM (#486698) Journal

    MIT Researchers Reveal More Efficient Way To Build Chips Below The 10nm Process []

    MIT researchers developed a new technique that allows chip structures to “self-assemble” at microscopic levels. The technique is said to be more cost-effective than extreme ultraviolet (EUV) lithography, another technique used in chip fabrication that’s expected to be used in 7nm and 5nm chips around 2020 or later.

    [...] A team of MIT researchers have developed a new technique called Direct Self-Assembly (DSA). This technique may help chip makers, especially those skeptical about EUV’s practicality in the short-term, to create 7nm or smaller chips.

    [...] According to the MIT team, the new process can be implemented using existing machinery with only small changes. This could make the technology more appealing to chip manufacturers, compared to using new lithography techniques to print much finer patterns.

    [...] One roadblock that the DSA technique could face is the fact that the lines formed by the chemical reactions may form structures that are too regular. The DSA technique may not work very well for chips with more irregular patterns, such as CPUs, but may work well enough for chips with much more regular patterns, such as memory chips.

    [SIG] 10/28/2017: Soylent Upgrade v14 []
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  • (Score: 2) by Azuma Hazuki on Thursday March 30 2017, @07:52PM (2 children)

    by Azuma Hazuki (5086) on Thursday March 30 2017, @07:52PM (#486699) Journal

    Oh, thank God. EUV isn't anywhere near ready and this may be just what the doctor ordered to give standard etching another generation or two...

    I am "that girl" your mother warned you about...
    • (Score: 2) by kaszz on Thursday March 30 2017, @08:07PM (1 child)

      by kaszz (4211) on Thursday March 30 2017, @08:07PM (#486714) Journal

      Why is EUV so bad?

      • (Score: 3, Informative) by takyon on Thursday March 30 2017, @08:32PM

        by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday March 30 2017, @08:32PM (#486733) Journal

        It's hard and expensive as heck, and 450mm wafers were supposed to make the transition to EUV easier, but haven't materialized.

        Intel's "Tick-Tock" Strategy Stalls, 10nm Chips Delayed []

        Intel will not be relying on the long-delayed extreme ultraviolet (EUV) lithography to make 10nm chips.

        Extreme ultraviolet lithography []

        What's the impact of 450-mm and EUV delays? [] (2010)

        This is what the death of Moore’s law looks like: EUV rollout slowed, 450mm wafers halted, and an uncertain path beyond 14nm [] (2014)

        One of the single greatest problems is source power. To put this simply — no one, including ASML, has yet demonstrated an EUV tool capable of reaching anything like the necessary power concentrations or of sustaining production volumes. Instead, we’re stuck at the red dot shown above. The enormous costs of shifting to EUV and 450mm wafers were meant to be partly offset by making the jump at the same time.

        Why EUV Is So Difficult []

        As it turns out, EUV is more difficult to master than previously thought. In fact, it’s arguably the most complex piece of machinery in the history of the IC industry.

        In EUV, a power source converts plasma into light at 13.5nm wavelengths. Then the light bounces off several mirrors before hitting the wafer. Today, EUV can print tiny features on a wafer, but the big problem is the power source—it doesn’t generate enough power to enable an EUV scanner go fast enough or make it economically feasible. In fact, there have been several delays with the source, causing EUV to get pushed out from one node to the next.

        The tide is slowly turning, however. In fact, the confidence level is gradually increasing for EUV in the industry, according to a recent survey from the eBeam Initiative. Moreover, ASML, the sole supplier of EUV scanners, is making progress with the power source. The EUV resists and masks are also improving. But issues remain involving tool costs, uptime and so-called stochastic phenomena.

        All told, EUV is expected to be ready for mass production by 2018 or 2019. If that happens, the industry must get its arms around the technology. But it also must be prepared if EUV stumbles again, which is also possible.

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