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posted by martyb on Saturday April 08 2017, @11:23PM   Printer-friendly
from the if-spammers-used-'em-would-we-have-phish-and-chips? dept.

This week Google released a report detailing the design and performance characteristics of the Tensor Processing Unit (TPU), its custom ASIC for the inference phase of neural networks (NN). Google has been using the machine learning accelerator in its datacenters since 2015, but hasn't said much about the hardware until now.

In a blog post published yesterday (April 5, 2017), Norm Jouppi, distinguished hardware engineer at Google, observes, "The need for TPUs really emerged about six years ago, when we started using computationally expensive deep learning models in more and more places throughout our products. The computational expense of using these models had us worried. If we considered a scenario where people use Google voice search for just three minutes a day and we ran deep neural nets for our speech recognition system on the processing units we were using, we would have had to double the number of Google data centers!"

The paper, "In-Datacenter Performance Analysis of a Tensor Processing Unit​," (the joint effort of more than 70 authors) describes the TPU thusly:

"The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power."


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  • (Score: 4, Insightful) by fishybell on Sunday April 09 2017, @12:20AM (4 children)

    by fishybell (3156) Subscriber Badge on Sunday April 09 2017, @12:20AM (#491015)

    I'm sure as more and more large companies with large datacenters start looking at these results you'll see more of them jump on the ASIC bandwagon. Given a large enough requirement for the same type of operation over and over, ASICs will always win out in the long run. We've seen it with Bitcoin, and now we're seeing it with datacenters. The fact that it's doing neural-net calculations is completely irrelevant.

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  • (Score: 1, Redundant) by Ethanol-fueled on Sunday April 09 2017, @01:01AM (1 child)

    by Ethanol-fueled (2792) on Sunday April 09 2017, @01:01AM (#491023) Homepage

    In case anybody asks why ASICs aren't used more, it's because they're way expensive compared to, say, an FPGA or CPLD. It wouldn't make sense to order just 20 of them unless you're fucking Google and possess the required Jew Golds.

    • (Score: 0) by Anonymous Coward on Tuesday April 11 2017, @05:07PM

      by Anonymous Coward on Tuesday April 11 2017, @05:07PM (#492358)

      Why are you so afraid of jews to the point where you have to spout tired cartman-esque nonsense? What, they killed your family and burnt down your village or something?

  • (Score: 2) by RamiK on Sunday April 09 2017, @08:44AM

    by RamiK (1813) on Sunday April 09 2017, @08:44AM (#491121)

    The fact that it's doing neural-net calculations is completely irrelevant.

    Yup. Once everyone sees how efficient my orthodontist's distal cutters are, they'll all want their own specialized, custom-made tools. CNC always wins out in the long run.

    --
    compiling...
  • (Score: 2) by kaszz on Sunday April 09 2017, @06:49PM

    by kaszz (4211) on Sunday April 09 2017, @06:49PM (#491227) Journal

    So how much does a ASIC cost these days?

    Say 130 nm process, 2 million transistors?