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posted by on Monday May 01 2017, @12:01PM   Printer-friendly
from the faster-is-better dept.

SK Hynix is almost ready to produce GDDR6 memory with higher than expected per-pin bandwidth:

In a surprising move, SK Hynix has announced its first memory chips based on the yet-unpublished GDDR6 standard. The new DRAM devices for video cards have capacity of 8 Gb and run at 16 Gbps per pin data rate, which is significantly higher than both standard GDDR5 and Micron's unique GDDR5X format. SK Hynix plans to produce its GDDR6 ICs in volume by early 2018.

GDDR5 memory has been used for top-of-the-range video cards for over seven years, since summer 2008 to present. Throughout its active lifespan, GDDR5 increased its data rate by over two times, from 3.6 Gbps to 9 Gbps, whereas its per chip capacities increased by 16 times from 512 Mb to 8 Gb. In fact, numerous high-end graphics cards, such as NVIDIA's GeForce GTX 1060 and 1070, still rely on the GDDR5 technology, which is not going anywhere even after the launch of Micron's GDDR5X with up to 12 Gbps data rate per pin in 2016. As it appears, GDDR6 will be used for high-end graphics cards starting in 2018, just two years after the introduction of GDDR5X.

Previously: Samsung Announces Mass Production of HBM2 DRAM
DDR5 Standard to be Finalized by JEDEC in 2018


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  • (Score: 2) by VLM on Monday May 01 2017, @03:09PM

    by VLM (445) on Monday May 01 2017, @03:09PM (#502288)

    Aside from all this desktop stuff, in the server and virtualization host market, nobody ever said their memory bus was too fast.

    From an engineering standpoint it should be possible to make optimizations such that sequential reading is kinda the default and faster at the expense of totally random access. Remember "Row and column" strobes for dram addressing in the 80s or so, you could extend that concept way beyond 2 dimensions (not physically of course?) such that sequential access would require usually 1 or sometimes 2 address segment writes per cycle for a graphics display but totally randomly smacking some random address would take like 8 address segment loads. Like imagine 128 parallel data lines and 8 bits of address and a whole bunch of segment strobes to load up the address 8 bits at a time. I wonder if there's also some weird dual porting stuff going on such that it wouldn't really be your first choice for a CPU.

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