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SK Hynix is almost ready to produce GDDR6 memory with higher than expected per-pin bandwidth:
In a surprising move, SK Hynix has announced its first memory chips based on the yet-unpublished GDDR6 standard. The new DRAM devices for video cards have capacity of 8 Gb and run at 16 Gbps per pin data rate, which is significantly higher than both standard GDDR5 and Micron's unique GDDR5X format. SK Hynix plans to produce its GDDR6 ICs in volume by early 2018.
GDDR5 memory has been used for top-of-the-range video cards for over seven years, since summer 2008 to present. Throughout its active lifespan, GDDR5 increased its data rate by over two times, from 3.6 Gbps to 9 Gbps, whereas its per chip capacities increased by 16 times from 512 Mb to 8 Gb. In fact, numerous high-end graphics cards, such as NVIDIA's GeForce GTX 1060 and 1070, still rely on the GDDR5 technology, which is not going anywhere even after the launch of Micron's GDDR5X with up to 12 Gbps data rate per pin in 2016. As it appears, GDDR6 will be used for high-end graphics cards starting in 2018, just two years after the introduction of GDDR5X.
Previously: Samsung Announces Mass Production of HBM2 DRAM
DDR5 Standard to be Finalized by JEDEC in 2018
(Score: 2) by shortscreen on Monday May 01 2017, @08:22PM
Pentium 3s were terribly memory speed limited. In some cases there was hardly any difference between a P3 800MHz or 1.4GHz if they both had PC-133 SDRAM. This was when Intel started building their shitty graphics into the motherboard chipset, so refreshing the display would eat up precious memory bandwidth. Changing the screen mode to a lower resolution and color depth to reduce bus contention would speed things up measurably. Check out these benchmark results from super pi:
Pentium 3 Coppermine 933MHz (discrete video card) - 2m17s
Pentium 3 Tualitin 800MHz (i830 graphics) - 2m35s
Pentium 3 Tualitin 1.33GHz (i830 graphics) - 2m20s
1.33GHz with lower latency 3-2-2 RAM - 2m06s
1.33GHz with screen mode set to 800x600 16-bit - 1m57s
Athlon XPs were also somewhat limited. Although they used DDR, since speeds eventually got up to 2.3GHz or so, on a 200MHz bus the latency got to be even worse than Pentium 3s (but with 64-byte line size instead of 32)
Athlon 64s and Pentium Ms greatly reduced this bottleneck by lowering latency and improving cache hit rates, respectively.
The weird thing is that the MOVSD instruction has never been optimized enough for a simple block copy to acheive anything close to theoretical memory throughput. It's always limited by the CPU instead (and read-before-write memory access patterns). I guess new CPUs have a fancier way to do block copies although I have not tried it.