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Samsung has added a so-called "4nm" process to its roadmap:
At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.
[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.
[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.
But how many transistors per square millimeter is it?
(Score: 2) by FatPhil on Monday June 05 2017, @10:37AM
Because Samsung are a small cash-strapped company who can't afford a proof-reader who is familiar with technology, yeah, right.
I shouldn't be surprised, even the contract I signed with SR-UK (Samsung Research UK) was in pretty mangled English.
Even Moore's English is a bit mangled, I'm sure he's talking about minimum cost per unit of functionality, which isn't the absolute minimum cost. MCUs are typically built on what might be considered very legacy processes (I guess 60-90, but I'm a bit out of touch), but they're not designed to have much functionality at all. Smaller than the smallest package size simply isn't worth it.
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