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posted by n1 on Thursday June 22 2017, @08:09AM   Printer-friendly
from the epyc-to-ynfynyty dept.

AMD has launched its Ryzen-based take on x86 server processors to compete with Intel's Xeon CPUs. All of the Epyc 7000-series CPUs support 128 PCIe 3.0 lanes and 8 channels (2 DIMMs per channel) of DDR4-2666 DRAM:

A few weeks ago AMD announced the naming of the new line of enterprise-class processors, called EPYC, and today marks the official launch with configurations up to 32 cores and 64 threads per processor. We also got an insight into several features of the design, including the AMD Infinity Fabric.

Today's announcement of the AMD EPYC product line sees the launch of the top four CPUs, focused primarily at dual socket systems. The full EPYC stack will contain twelve processors, with three for single socket environments, with the rest of the stack being made available at the end of July. It is worth taking a few minutes to look at how these processors look under the hood.

On the package are four silicon dies, each one containing the same 8-core silicon we saw in the AMD Ryzen processors. Each silicon die has two core complexes, each of four cores, and supports two memory channels, giving a total maximum of 32 cores and 8 memory channels on an EPYC processor. The dies are connected by AMD's newest interconnect, the Infinity Fabric, which plays a key role not only in die-to-die communication but also processor-to-processor communication and within AMD's new Vega graphics. AMD designed the Infinity Fabric to be modular and scalable in order to support large GPUs and CPUs in the roadmap going forward, and states that within a single package the fabric is overprovisioned to minimize any issues with non-NUMA aware software (more on this later).

With a total of 8 memory channels, and support for 2 DIMMs per channel, AMD is quoting a 2TB per socket maximum memory support, scaling up to 4TB per system in a dual processor system. Each CPU will support 128 PCIe 3.0 lanes, suitable for six GPUs with full bandwidth support (plus IO) or up to 32 NVMe drives for storage. All the PCIe lanes can be used for IO devices, such as SATA drives or network ports, or as Infinity Fabric connections to other devices. There are also 4 IO hubs per processor for additional storage support.

AMD's slides at Ars Technica.

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  • (Score: 4, Informative) by Alphatool on Thursday June 22 2017, @11:31AM (2 children)

    by Alphatool (1145) on Thursday June 22 2017, @11:31AM (#529463)

    The new security features [] on these chips are really interesting too. In particular, the secure memory encryption (making physical attacks on a machine much harder) and secure encrypted virtualization (allowing memory access for virtual machines without the hypervisor being able to read it) will be a big step forward in some environments. It's not perfect, but it's much better than the current alternative, which is nothing.

    There is one massive asterisk next to this though - it's fully dependent on a closed source ARM micro controller built into the chip. If there is a vulnerability or a back door in that then it's game over. How much do you trust AMD?

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  • (Score: 2, Insightful) by The Mighty Buzzard on Thursday June 22 2017, @11:37AM

    About as much as I trust Intel. Which is to say I'm fairly certain they've long since handed the NSA the keys to the kingdom and if not they will be doing so soon.

    My rights don't end where your fear begins.
  • (Score: 3, Insightful) by iwoloschin on Thursday June 22 2017, @07:59PM

    by iwoloschin (3863) on Thursday June 22 2017, @07:59PM (#529637)

    If AMD is paying any attention they'll let big customers review the ARM ┬ÁC's source code under NDA.