Stories
Slash Boxes
Comments

SoylentNews is people

posted by Fnord666 on Wednesday July 05 2017, @06:21PM   Printer-friendly
from the profit-earnings-ratio dept.

While QLC NAND is predicted to have as low as 100 program/erase cycles (endurance), Toshiba has "targeted" 1000 cycles for its upcoming 3D QLC NAND products:

Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.

[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:

- What's the number of P/E cycles supported by Toshiba's QLC NAND?
- QLC P/E is targeted for 1K cycles.

Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?

[Ed. note: If you're wondering what QLC NAND is, here's a quick primer.]

Additional Coverage: The guru of 3D


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 4, Insightful) by kaszz on Wednesday July 05 2017, @07:08PM (6 children)

    by kaszz (4211) on Wednesday July 05 2017, @07:08PM (#535354) Journal

    Regular EEPROM is on the order of 100 000 writes and 10 years retention. A memory used as secondary storage "disc" ought to have way more write cycles to be viable.

    Maybe I'm missing something fundamental here. But currently this memory seems to fit the role of a mostly read only cache for often used data and boot code.

    Starting Score:    1  point
    Moderation   +2  
       Insightful=2, Total=2
    Extra 'Insightful' Modifier   0  
    Karma-Bonus Modifier   +1  

    Total Score:   4  
  • (Score: 3, Informative) by takyon on Wednesday July 05 2017, @07:27PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday July 05 2017, @07:27PM (#535369) Journal

    There are numerous 3D TLC NAND SSDs out there. Typical warranty for TLC seems to be three [tomsitpro.com] years [anandtech.com]. If QLC NAND can somehow match the endurance of TLC, then it could work just fine.

    The massive capacity of 3D NAND SSDs can allow for overprovisioning to keep the capacity usable.

    If you don't need multiple drive writes per day, or if you treat it like write-once-read-many "cold storage", then there won't necessarily be a problem. Capacity/$ is what is desired for this storage tier, not stellar endurance.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
  • (Score: 2) by fnj on Thursday July 06 2017, @04:26PM (4 children)

    by fnj (1654) on Thursday July 06 2017, @04:26PM (#535772)

    Five years ago they already knew how to make NAND flash with at least 100 MILLION P/E cycles [ieee.org]! What the hell happened to that tech?

    • (Score: 2) by takyon on Thursday July 06 2017, @06:10PM (3 children)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday July 06 2017, @06:10PM (#535810) Journal

      It was probably too expensive and became abandoned once 3D/vertical NAND eliminated the "endurance wall".

      --
      [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 2) by kaszz on Thursday July 06 2017, @09:35PM (2 children)

        by kaszz (4211) on Thursday July 06 2017, @09:35PM (#535889) Journal

        How can vertical NAND eliminate a 100 write limit? that is like 4 magnitudes worse performance..

        • (Score: 2) by takyon on Thursday July 06 2017, @10:08PM (1 child)

          by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday July 06 2017, @10:08PM (#535906) Journal

          http://www.anandtech.com/show/8239/update-on-samsung-850-pro-endurance-vnand-die-size [anandtech.com]

          http://www.tomsitpro.com/articles/samsung-pm863-3d-tlc-v-nand-ssd,2-958.html [tomsitpro.com]

          3D NAND steps back to a larger lithography than its planar counterparts do, which imparts enough endurance to ensure that 3D TLC NAND is a reliable solution.

          Also overprovisioning [kingston.com] which there is more room to do with vertical.

          --
          [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
          • (Score: 2) by kaszz on Saturday July 08 2017, @02:40AM

            by kaszz (4211) on Saturday July 08 2017, @02:40AM (#536378) Journal

            The explanation on how they succeed with real life re-write endurance when looking past the overprovisioning is still not explained. The closest I have read is some Taiwanese engineers coming up with a heating method to make bad cells anneal and accomplish 100 million re-write performance.

            In the end it seems these kinds of memories are good for some specific use cases. Mechanical harddiscs still have a major durability advantage. Laptops may be a special case. But reliance on electrical charge + gamma scanners at airports or electrical disruptive environments seems risky. And when they crash it's a hard one.