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While QLC NAND is predicted to have as low as 100 program/erase cycles (endurance), Toshiba has "targeted" 1000 cycles for its upcoming 3D QLC NAND products:
Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.
[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:
- What's the number of P/E cycles supported by Toshiba's QLC NAND?
- QLC P/E is targeted for 1K cycles.
Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?
[Ed. note: If you're wondering what QLC NAND is, here's a quick primer.]
Additional Coverage: The guru of 3D
(Score: 2) by kaszz on Saturday July 08 2017, @02:40AM
The explanation on how they succeed with real life re-write endurance when looking past the overprovisioning is still not explained. The closest I have read is some Taiwanese engineers coming up with a heating method to make bad cells anneal and accomplish 100 million re-write performance.
In the end it seems these kinds of memories are good for some specific use cases. Mechanical harddiscs still have a major durability advantage. Laptops may be a special case. But reliance on electrical charge + gamma scanners at airports or electrical disruptive environments seems risky. And when they crash it's a hard one.