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posted by
martyb
on Thursday November 30 2017, @09:35AM
from the whatever-will-they-do-with-the-one-billion-leftover-apples? dept.
from the whatever-will-they-do-with-the-one-billion-leftover-apples? dept.
From a Western Digital press release:
Western Digital Corp. (NASDAQ: WDC) announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to [...] transitioning its own consumption of processors – over one billion cores per year – to RISC-V.
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Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V
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Your step will soil many countries.
(Score: 3, Informative) by takyon on Thursday November 30 2017, @11:02AM (2 children)
How WD Plans to Lead Major Changeover to RISC-V Processing [eweek.com]
RISC-V Spins into Drives, AI [eetimes.com]
Big Tech Players Start To Adopt The RISC-V Chip Architecture [tomshardware.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by JoeMerchant on Thursday November 30 2017, @12:58PM
So, I'm lazy, but... assuming they are transitioning away from ARM? Watch this space: https://finance.yahoo.com/quote/SFTBY?ltr=1 [yahoo.com] for a reaction to the news.
🌻🌻🌻🌻 [google.com]
(Score: 0) by Anonymous Coward on Thursday November 30 2017, @04:48PM
in the third link it said that nvidia will be moving to risk for their GPU microcontrollers. it's going to feel weird moving to all nvidia, assuming they helped more with nouveau...
(Score: 3, Interesting) by Wootery on Thursday November 30 2017, @12:02PM (12 children)
Real industry adoption, by a major player, doing mission-critical work in their core products. Great stuff.
Here's to a long and varied future of success for RISC-V. [Raises mug]
(Score: 3, Funny) by takyon on Thursday November 30 2017, @12:32PM (9 children)
Can we say "RISCY business"? "RISC-V business"?
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(Score: 1, Interesting) by Anonymous Coward on Thursday November 30 2017, @01:38PM (2 children)
"RISQUE Business"?
(Score: 2) by Wootery on Thursday November 30 2017, @02:08PM (1 child)
Eh? Is RISQUE an acronym?
(Score: 2) by DannyB on Thursday November 30 2017, @03:44PM
RISC-V Quality User Experience
RISC-V Quality Useful Exceptional
Why do we need long double when a 64 bit double already represents all possible real numbers?
(Score: 2) by Wootery on Thursday November 30 2017, @02:10PM (5 children)
Don't give them ideas - next thing we know we'll have a RISC management engine.
(Score: 4, Funny) by DannyB on Thursday November 30 2017, @03:46PM (3 children)
Maybe we do already and we just don't know it. Or maybe that's what they want you to think. Or maybe Obama's birth certificate was signed using a weak cryptographic key. Or maybe the aliens are behind it.
Why do we need long double when a 64 bit double already represents all possible real numbers?
(Score: 2) by bob_super on Thursday November 30 2017, @06:20PM (2 children)
> birth certificate was signed using a weak cryptographic key
New geek idea: The same way that nobles and Chinese people used to seal or sign stuff with custom stamps, I'm gonna get stamps made with the customer's Public Key to sign official papers, checks and letters.
Patent pending.
(Score: 2) by takyon on Thursday November 30 2017, @06:33PM (1 child)
I hope you can fit all 16,384 bits on there.
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(Score: 2) by bob_super on Thursday November 30 2017, @06:39PM
https://www.rubberstamps.net/ProductDetail.aspx?ProductID=WOODSTAMP16 [rubberstamps.net]
alternatively:
https://tufel.files.wordpress.com/2008/02/big-stamp.jpg [wordpress.com]
(Score: 2) by RamiK on Thursday November 30 2017, @08:48PM
The sanctums proposal satisfies remote computing and DRM: https://www.youtube.com/watch?v=K3EN0_g6yL4 [youtube.com]
There are recent attempts at formal verification: https://people.eecs.berkeley.edu/~rsinha/research/pubs/ccs2017.pdf [berkeley.edu]
It's basically a cleaned up SGX that could allow a per-machine key to be issued by the silicon manufacturers as a CA. But the enclave is isolated and can't access anything the OS hasn't allocated it.
The nice thing about this design is that, if you choose to, it will let you reject any enclave requests or just approve specific requests through the OS. While, at the same time, it has no persistent code running in the background that is outside your control as long as there aren't any enclaves running. This can also be verified easily by measuring power and/or thermal imaging the die while idling.
compiling...
(Score: 3, Insightful) by driverless on Friday December 01 2017, @12:49AM (1 child)
Real press release, by a major player currently renegotiating their Arm license. Commercially astute stuff.
(Score: 2) by Wootery on Friday December 01 2017, @10:34AM
Fair points, but did OpenRISC ever see this kind of success?
(Score: 2) by Rich on Thursday November 30 2017, @09:35PM
We can be happy every time such a libre solution scores a design win and gets a bit more entrenched.
I'm wondering what strings have been pulled behind the scenes. I've been dabbling in the world of DLX-descendents, particularly with a bit of work on the Microblaze Linux port for a vertical market customer, and have been aware of the developments. (To those who haven't heard of DLX or Hennessy/Patterson-Architecture, it's kind of the idea seed for the MIPS like architectures, Microblaze, OpenRISC and now RISC-V).
So there is already a libre contender in this area (OpenRISC), even being used commercially (Samsung). The RISC-V guys are late to the party. They pull an NIH (yeah, i've seen their arguments...), deliver something which looks a tad too seasoned for an academic project, and soon after score a 1bn/a units design win.
It will be interesting to watch that space.