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posted by martyb on Thursday February 01 2018, @07:16AM   Printer-friendly
from the you-are-in-a-maze-of-tiny-little-transistors-all-alike dept.

Taiwan Semiconductor Manufacturing Company (TSMC) plans to make so-called "5nm" chips starting in early 2020:

TSMC last week held a groundbreaking ceremony for its Fab 18 phase 1 production facility. The fab will produce chips using TSMC's 5 nm process starting from early 2020. When all three phases of the manufacturing facility are completed, its wafer starts capacity will exceed one million 300-mm wafers per year, comparable with other three GigaFabs operated by TSMC.

TSMC's Fab 18 will be located in Tainan (in the Southern Taiwan Science Park), and will be built in three phases. The construction of the first phase or segment of the building will be completed in about a year from now, after which TSMC will move in equipment sometime in early 2019. In about two years from now, the company expects to start volume production of chips using its 5 nm process technology at the Fab 18/phase 1. Construction of the second and the third phases will commence in Q3 2018 and Q3 2019. The two phases will start volume production in 2020 and 2021, respectively.

Extreme ultraviolet (EUV) lithography could be used to make "7nm" chips, but not "5nm" yet.

Related: Samsung's 10nm Chips in Mass Production, "6nm" on the Roadmap
Moore's Law: Not Dead? Intel Says its 10nm Chips Will Beat Samsung's
Samsung Plans a "4nm" Process
GlobalFoundries to Spend $10-12 Billion on a 7nm Fab, Possibly $14-18 Billion for 5nm


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  • (Score: 2) by TheRaven on Thursday February 01 2018, @10:11AM (1 child)

    by TheRaven (270) on Thursday February 01 2018, @10:11AM (#631400) Journal
    Anyone remember back in the days when the size for a process meant the size of the smallest feature, or even further back when it meant the size of something actually useful, rather than just a 'hey, look, I have a smaller number than you!' marketing thing?
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  • (Score: 0) by Anonymous Coward on Thursday February 01 2018, @11:47AM

    by Anonymous Coward on Thursday February 01 2018, @11:47AM (#631430)

    I thought it meant the size of the conductive tracks between components on the chip.