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posted by Fnord666 on Monday May 14 2018, @10:25PM   Printer-friendly
from the hot-tech dept.

The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:

Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.

One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.

Not discussed is how to deal with the heat generated in such a stack.

See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs


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  • (Score: 4, Interesting) by Snotnose on Monday May 14 2018, @10:53PM (4 children)

    by Snotnose (1623) on Monday May 14 2018, @10:53PM (#679807)

    Some 10-15 years ago Qualcomm had a package that consisted of a FLASH chip sitting on top of the radio chip which sat on top of the baseband chip. SC2x or something.

    I suspect the big problem here will be heat. When you have to put a big honkin heatsink on both your CPU and GPU whattaya gonna do, put a heat sink on both sides of the package? Run tubes for water cooling?

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  • (Score: 2) by takyon on Monday May 14 2018, @11:05PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Monday May 14 2018, @11:05PM (#679812) Journal

    Flash chips are a lot cooler, and 64-layer 3D NAND is available now.

    Even a "2-layer" CPU or GPU would be a big change.

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  • (Score: 0) by Anonymous Coward on Tuesday May 15 2018, @01:30AM

    by Anonymous Coward on Tuesday May 15 2018, @01:30AM (#679879)

    https://www.youtube.com/watch?v=YpphKzmDiJM [youtube.com]

    That may be a possible solution if it works as well as they are claiming in that video. QCOM got away with what they did at the time because it was a SoC for a phone that ran for 10+ days on 1 charge. Not exactly high voltage and max heat disp there. In the div I worked in we did not even bother with a heatsink on them.

  • (Score: 3, Insightful) by driverless on Tuesday May 15 2018, @01:30AM (1 child)

    by driverless (4770) on Tuesday May 15 2018, @01:30AM (#679880)

    My immediate response as well, the title should be:

    Dual-Wafer Packaging (Wafer-on-Wafer) Could Double CPU/GPU Heat Output

    Stacking only works when you've got parts with relatively low heat output, e.g. a flash, older CPU, RAM stack. A CPU, CPU stack is just an expensive oven element.

    • (Score: 2) by TheRaven on Wednesday May 16 2018, @05:27AM

      by TheRaven (270) on Wednesday May 16 2018, @05:27AM (#680292) Journal
      I'd add to that: Moore's law is still more or less working, but Dennard Scaling has not for about 10 years. We can currently (cheaply) put more transistors on a chip than we can power / cool at the same time and that's been true for a while. Anything that increases density without improving cooling or decreasing power consumption is likely to be a waste of time. This might be useful for RAM, which tends to be manufactured using different processes and so is difficult to put on the same wafer, but CPUs and GPUs can easily be put on the same chip if you don't care about heat / power.
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